Commit 78effb4a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-08-26-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Weekly fixes, lots of amdgpu fixes mostly for IP blocks introduced in
  6.0-rc1, otherwise vc4, nouveau fixes.

  gem:
   - Fix handle release leak

  nouveau:
   - Fix fencing when moving BO

  vc4:
   - HDMI fixes

  amdgpu:
   - GFX 11.0 fixes
   - PSP XGMI handling fixes
   - GFX9 fix for compute-only IPs
   - Drop duplicated function call
   - Fix warning due to missing header
   - NBIO 7.7 fixes
   - DCN 3.1.4 fixes
   - SDMA 6.0 fixes
   - SMU 13.0 fixes
   - Arcturus GPUVM page table fix
   - MMHUB 1.0 fix

  amdkfd:
   - GC 10.3.7 fix

  radeon:
   - Delayed work flush fix"

* tag 'drm-fixes-2022-08-26-1' of git://anongit.freedesktop.org/drm/drm: (21 commits)
  drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly
  drm/amdgpu: add MGCG perfmon setting for gfx11
  drm/amdkfd: Fix isa version for the GC 10.3.7
  drm/amdgpu: Fix page table setup on Arcturus
  drm/amd/pm: update SMU 13.0.0 driver_if header
  drm/amdgpu: add sdma instance check for gfx11 CGCG
  drm/amd/display: enable PCON support for dcn314
  drm/amdgpu: enable NBIO IP v7.7.0 Clock Gating
  drm/amdgpu: add NBIO IP v7.7.0 Clock Gating support
  drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0
  nouveau: explicitly wait on the fence in nouveau_bo_move_m2mf
  drm/radeon: add a force flush to delay work when radeon
  drm/amd/display: Include missing header
  drm/amdgpu: Remove the additional kfd pre reset call for sriov
  drm/amdgpu: Check num_gfx_rings for gfx v9_0 rb setup.
  drm/amdgpu: fix hive reference leak when adding xgmi device
  drm/amdgpu: Move psp_xgmi_terminate call from amdgpu_xgmi_remove_device to psp_hw_fini
  drm/amdgpu: enable GFXOFF allow control for GC IP v11.0.1
  drm/gem: Fix GEM handle release errors
  drm/vc4: hdmi: Rework power up
  ...
parents 3e5c673f 100d0ae8

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −2
Original line number Diff line number Diff line
@@ -2456,12 +2456,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
			if (!hive->reset_domain ||

			    !amdgpu_reset_get_reset_domain(hive->reset_domain)) {

				r = -ENOENT;

				amdgpu_put_xgmi_hive(hive);

				goto init_failed;

			}



			/* Drop the early temporary reset domain we created for device */

			amdgpu_reset_put_reset_domain(adev->reset_domain);

			adev->reset_domain = hive->reset_domain;

			amdgpu_put_xgmi_hive(hive);

		}

	}
@@ -4413,8 +4415,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, 
retry:

	amdgpu_amdkfd_pre_reset(adev);



	amdgpu_amdkfd_pre_reset(adev);



	if (from_hypervisor)

		r = amdgpu_virt_request_full_gpu(adev, true);

	else

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −0
Original line number Diff line number Diff line
@@ -2641,6 +2641,9 @@ static int psp_hw_fini(void *handle) 
		psp_rap_terminate(psp);

		psp_dtm_terminate(psp);

		psp_hdcp_terminate(psp);



		if (adev->gmc.xgmi.num_physical_nodes > 1)

			psp_xgmi_terminate(psp);

	}



	psp_asd_terminate(psp);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

+1 −1
Original line number Diff line number Diff line
@@ -742,7 +742,7 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 
		amdgpu_put_xgmi_hive(hive);

	}



	return psp_xgmi_terminate(&adev->psp);

	return 0;

}



static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+16 −8
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 
					   bool all_hub, uint8_t dst_sel);

static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);

static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);

static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,

				      bool enable);



static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)

{
@@ -1139,6 +1141,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 
	.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,

	.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,

	.init_spm_golden = &gfx_v11_0_init_spm_golden_registers,

	.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,

};



static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
@@ -5182,9 +5185,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 
		data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);



		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */

		if (adev->sdma.num_instances > 1) {

			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

			data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);

		}

	} else {

		/* Program RLC_CGCG_CGLS_CTRL */

		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
@@ -5213,11 +5219,14 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 
		data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);



		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */

		if (adev->sdma.num_instances > 1) {

			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

			data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);

		}

	}

}



static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,

					    bool enable)
@@ -5328,8 +5337,7 @@ static int gfx_v11_0_set_powergating_state(void *handle, 
		break;

	case IP_VERSION(11, 0, 1):

		gfx_v11_cntl_pg(adev, enable);

		/* TODO: Enable this when GFXOFF is ready */

		// amdgpu_gfx_off_ctrl(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);

		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -2587,6 +2587,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 


	gfx_v9_0_tiling_mode_table_init(adev);



	if (adev->gfx.num_gfx_rings)

		gfx_v9_0_setup_rb(adev);

	gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);

	adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);