Commit 78f2c089 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a08g045: Add ADC node 



Add the device tree node for the ADC IP available on the Renesas RZ/G3S
SoC.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241206111337.726244-15-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c4d87fe3

arch/arm64/boot/dts/renesas/r9a08g045.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -177,6 +177,59 @@ rtc: rtc@1004ec00 { 
			status = "disabled";

		};



		adc: adc@10058000 {

			compatible = "renesas,r9a08g045-adc";

			reg = <0 0x10058000 0 0x1000>;

			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;

			clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,

				 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;

			clock-names = "adclk", "pclk";

			resets = <&cpg R9A08G045_ADC_PRESETN>,

				 <&cpg R9A08G045_ADC_ADRST_N>;

			reset-names = "presetn", "adrst-n";

			power-domains = <&cpg>;

			#address-cells = <1>;

			#size-cells = <0>;

			#io-channel-cells = <1>;

			status = "disabled";



			channel@0 {

				reg = <0>;

			};



			channel@1 {

				reg = <1>;

			};



			channel@2 {

				reg = <2>;

			};



			channel@3 {

				reg = <3>;

			};



			channel@4 {

				reg = <4>;

			};



			channel@5 {

				reg = <5>;

			};



			channel@6 {

				reg = <6>;

			};



			channel@7 {

				reg = <7>;

			};



			channel@8 {

				reg = <8>;

			};

		};



		vbattb: clock-controller@1005c000 {

			compatible = "renesas,r9a08g045-vbattb";

			reg = <0 0x1005c000 0 0x1000>;