Commit 78f608d7 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Enable DCC on DCN401 



[WHAT]
Add registers and entry points to enable DCC on DCN4x

Reviewed-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2d072b44

drivers/gpu/drm/amd/display/dc/core/dc.c

+12 −0
Original line number Diff line number Diff line
@@ -1264,6 +1264,9 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 
				apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);

				dc->hwss.post_unlock_program_front_end(dc, dangling_context);

			}



			if (dc->res_pool->funcs->prepare_mcache_programming)

				dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);

			if (dc->hwss.program_front_end_for_ctx) {

				dc->hwss.interdependent_update_lock(dc, dc->current_state, true);

				dc->hwss.program_front_end_for_ctx(dc, dangling_context);
@@ -2037,6 +2040,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
	}



	/* Program all planes within new context*/

	if (dc->res_pool->funcs->prepare_mcache_programming)

		dc->res_pool->funcs->prepare_mcache_programming(dc, context);

	if (dc->hwss.program_front_end_for_ctx) {

		dc->hwss.interdependent_update_lock(dc, context, true);

		dc->hwss.program_front_end_for_ctx(dc, context);
@@ -3884,6 +3889,9 @@ static void commit_planes_for_stream(struct dc *dc, 
				odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;

	}



	if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)

		dc->res_pool->funcs->prepare_mcache_programming(dc, context);



	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

		if (top_pipe_to_program &&

			top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
@@ -3903,6 +3911,10 @@ static void commit_planes_for_stream(struct dc *dc, 
						top_pipe_to_program->stream_res.tg);

		}



	if (dc->hwss.wait_for_dcc_meta_propagation) {

		dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);

	}



	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

		if (dc->hwss.subvp_pipe_control_lock)

			dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

+11 −0
Original line number Diff line number Diff line
@@ -595,6 +595,12 @@ void hwss_build_fast_sequence(struct dc *dc, 
	if (!plane || !stream)

		return;



	if (dc->hwss.wait_for_dcc_meta_propagation) {

		block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

		block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;

		block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;

		(*num_steps)++;

	}

	if (dc->hwss.subvp_pipe_control_lock_fast) {

		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
@@ -835,6 +841,11 @@ void hwss_execute_sequence(struct dc *dc, 
		case DMUB_SUBVP_SAVE_SURF_ADDR:

			hwss_subvp_save_surf_addr(params);

			break;

		case HUBP_WAIT_FOR_DCC_META_PROP:

			dc->hwss.wait_for_dcc_meta_propagation(

					params->wait_for_dcc_meta_propagation_params.dc,

					params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);

			break;

		case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:

			dc->hwss.fams2_global_control_lock_fast(params);

			break;

drivers/gpu/drm/amd/display/dc/dc.h

+4 −0
Original line number Diff line number Diff line
@@ -333,6 +333,9 @@ struct dc_dcc_setting { 
		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN 3.0

		uint32_t dcc_256_128_128 : 1;		//available starting with DCN 3.0

		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN 3.0 (the best compression case)

		uint32_t dcc_256_256 : 1;  //available in ASICs starting with DCN 4.0x (the best compression case)

		uint32_t dcc_256_128 : 1;  //available in ASICs starting with DCN 4.0x

		uint32_t dcc_256_64 : 1;   //available in ASICs starting with DCN 4.0x (the worst compression case)

	} dcc_controls;

};
@@ -1037,6 +1040,7 @@ struct dc_debug_options { 
	unsigned int static_screen_wait_frames;

	uint32_t pwm_freq;

	bool force_chroma_subsampling_1tap;

	unsigned int dcc_meta_propagation_delay_us;

	bool disable_422_left_edge_pixel;

	bool dml21_force_pstate_method;

	uint32_t dml21_force_pstate_method_values[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

+6 −0
Original line number Diff line number Diff line
@@ -821,6 +821,12 @@ void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, 
	*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];

}



void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)

{

	if (dml2->architecture == dml2_architecture_21)

		dml21_prepare_mcache_programming(in_dc, context, dml2);

}



void dml2_copy(struct dml2_context *dst_dml2,

	struct dml2_context *src_dml2)

{

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h

+1 −1
Original line number Diff line number Diff line
@@ -303,5 +303,5 @@ bool dml2_validate(const struct dc *in_dc, 
 */

void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,

	unsigned int *fclk_change_support, unsigned int *dram_clk_change_support);



void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);

#endif //_DML2_WRAPPER_H_