Commit 78fe51fc authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/cadence' 

- Add j721e DT and driver support for 'num-lanes' for devices that support
  x1, x2, or x4 Links (Matt Ranostay)

- Add j721e DT compatible strings and driver support for j784s4 (Matt Ranostay)

- Make TI J721E Kconfig depend on ARCH_K3 since the hardware is specific to
  those TI SoC parts (Peter Robinson)

* pci/controller/cadence:
  PCI: j721e: Make TI J721E depend on ARCH_K3
  PCI: j721e: Add TI J784S4 PCIe configuration
  PCI: j721e: Add PCIe 4x lane selection support
  PCI: j721e: Add per platform maximum lane settings
  dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings
  dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
parents 6f77f0ac 177c9ac6

Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

+36 −3
Original line number Diff line number Diff line
@@ -10,13 +10,11 @@ title: TI J721E PCI EP (PCIe Wrapper) 
maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>



allOf:

  - $ref: cdns-pcie-ep.yaml#



properties:

  compatible:

    oneOf:

      - const: ti,j721e-pcie-ep

      - const: ti,j784s4-pcie-ep

      - description: PCIe EP controller in AM64

        items:

          - const: ti,am64-pcie-ep
@@ -65,6 +63,41 @@ properties: 
    items:

      - const: link_state



allOf:

  - $ref: cdns-pcie-ep.yaml#

  - if:

      properties:

        compatible:

          enum:

            - ti,am64-pcie-ep

    then:

      properties:

        num-lanes:

          const: 1



  - if:

      properties:

        compatible:

          enum:

            - ti,j7200-pcie-ep

            - ti,j721e-pcie-ep

    then:

      properties:

        num-lanes:

          minimum: 1

          maximum: 2



  - if:

      properties:

        compatible:

          enum:

            - ti,j784s4-pcie-ep

    then:

      properties:

        num-lanes:

          minimum: 1

          maximum: 4



required:

  - compatible

  - reg

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

+36 −3
Original line number Diff line number Diff line
@@ -10,13 +10,11 @@ title: TI J721E PCI Host (PCIe Wrapper) 
maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>



allOf:

  - $ref: cdns-pcie-host.yaml#



properties:

  compatible:

    oneOf:

      - const: ti,j721e-pcie-host

      - const: ti,j784s4-pcie-host

      - description: PCIe controller in AM64

        items:

          - const: ti,am64-pcie-host
@@ -94,6 +92,41 @@ properties: 
      interrupts:

        maxItems: 1



allOf:

  - $ref: cdns-pcie-host.yaml#

  - if:

      properties:

        compatible:

          enum:

            - ti,am64-pcie-host

    then:

      properties:

        num-lanes:

          const: 1



  - if:

      properties:

        compatible:

          enum:

            - ti,j7200-pcie-host

            - ti,j721e-pcie-host

    then:

      properties:

        num-lanes:

          minimum: 1

          maximum: 2



  - if:

      properties:

        compatible:

          enum:

            - ti,j784s4-pcie-host

    then:

      properties:

        num-lanes:

          minimum: 1

          maximum: 4



required:

  - compatible

  - reg

drivers/pci/controller/cadence/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ config PCI_J721E 


config PCI_J721E_HOST

	bool "TI J721E PCIe controller (host mode)"

	depends on ARCH_K3 || COMPILE_TEST

	depends on OF

	select PCIE_CADENCE_HOST

	select PCI_J721E
@@ -57,6 +58,7 @@ config PCI_J721E_HOST 


config PCI_J721E_EP

	bool "TI J721E PCIe controller (endpoint mode)"

	depends on ARCH_K3 || COMPILE_TEST

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE_EP

drivers/pci/controller/cadence/pci-j721e.c

+40 −5
Original line number Diff line number Diff line
@@ -42,18 +42,16 @@ enum link_status { 
};



#define J721E_MODE_RC			BIT(7)

#define LANE_COUNT_MASK			BIT(8)

#define LANE_COUNT(n)			((n) << 8)



#define GENERATION_SEL_MASK		GENMASK(1, 0)



#define MAX_LANES			2



struct j721e_pcie {

	struct cdns_pcie	*cdns_pcie;

	struct clk		*refclk;

	u32			mode;

	u32			num_lanes;

	u32			max_lanes;

	void __iomem		*user_cfg_base;

	void __iomem		*intd_cfg_base;

	u32			linkdown_irq_regfield;
@@ -71,6 +69,7 @@ struct j721e_pcie_data { 
	unsigned int		quirk_disable_flr:1;

	u32			linkdown_irq_regfield;

	unsigned int		byte_access_allowed:1;

	unsigned int		max_lanes;

};



static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -206,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 
{

	struct device *dev = pcie->cdns_pcie->dev;

	u32 lanes = pcie->num_lanes;

	u32 mask = BIT(8);

	u32 val = 0;

	int ret;



	if (pcie->max_lanes == 4)

		mask = GENMASK(9, 8);



	val = LANE_COUNT(lanes - 1);

	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);

	ret = regmap_update_bits(syscon, offset, mask, val);

	if (ret)

		dev_err(dev, "failed to set link count\n");
@@ -290,11 +293,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = { 
	.quirk_retrain_flag = true,

	.byte_access_allowed = false,

	.linkdown_irq_regfield = LINK_DOWN,

	.max_lanes = 2,

};



static const struct j721e_pcie_data j721e_pcie_ep_data = {

	.mode = PCI_MODE_EP,

	.linkdown_irq_regfield = LINK_DOWN,

	.max_lanes = 2,

};



static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -302,23 +307,41 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { 
	.quirk_detect_quiet_flag = true,

	.linkdown_irq_regfield = J7200_LINK_DOWN,

	.byte_access_allowed = true,

	.max_lanes = 2,

};



static const struct j721e_pcie_data j7200_pcie_ep_data = {

	.mode = PCI_MODE_EP,

	.quirk_detect_quiet_flag = true,

	.quirk_disable_flr = true,

	.max_lanes = 2,

};



static const struct j721e_pcie_data am64_pcie_rc_data = {

	.mode = PCI_MODE_RC,

	.linkdown_irq_regfield = J7200_LINK_DOWN,

	.byte_access_allowed = true,

	.max_lanes = 1,

};



static const struct j721e_pcie_data am64_pcie_ep_data = {

	.mode = PCI_MODE_EP,

	.linkdown_irq_regfield = J7200_LINK_DOWN,

	.max_lanes = 1,

};



static const struct j721e_pcie_data j784s4_pcie_rc_data = {

	.mode = PCI_MODE_RC,

	.quirk_retrain_flag = true,

	.byte_access_allowed = false,

	.linkdown_irq_regfield = LINK_DOWN,

	.max_lanes = 4,

};



static const struct j721e_pcie_data j784s4_pcie_ep_data = {

	.mode = PCI_MODE_EP,

	.linkdown_irq_regfield = LINK_DOWN,

	.max_lanes = 4,

};



static const struct of_device_id of_j721e_pcie_match[] = {
@@ -346,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { 
		.compatible = "ti,am64-pcie-ep",

		.data = &am64_pcie_ep_data,

	},

	{

		.compatible = "ti,j784s4-pcie-host",

		.data = &j784s4_pcie_rc_data,

	},

	{

		.compatible = "ti,j784s4-pcie-ep",

		.data = &j784s4_pcie_ep_data,

	},

	{},

};
@@ -432,9 +463,13 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
	pcie->user_cfg_base = base;



	ret = of_property_read_u32(node, "num-lanes", &num_lanes);

	if (ret || num_lanes > MAX_LANES)

	if (ret || num_lanes > data->max_lanes) {

		dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");

		num_lanes = 1;

	}



	pcie->num_lanes = num_lanes;

	pcie->max_lanes = data->max_lanes;



	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))

		return -EINVAL;