Commit 7959deaa authored by Gatien Chevallier's avatar Gatien Chevallier Committed by Linus Walleij
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pinctrl: stm32: handle semaphore acquisition when handling pinctrl/pinmux 



When a GPIO RIF configuration is in semaphore mode, and the semaphore
hasn't been taken before configuring the GPIO, the write operations
silently fail.

To avoid a silent fail when applying a pinctrl, if the pins that are
being configured are in semaphore mode, take the semaphore. Note that
there is no proper release of the RIF semaphore yet for pinctrl.

Signed-off-by: default avatarGatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent dbd2317d

drivers/pinctrl/stm32/pinctrl-stm32.c

+27 −8
Original line number Diff line number Diff line
@@ -362,11 +362,9 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 
		return -EINVAL;

	}



	if (bank->rif_control) {

		if (!stm32_gpio_rif_acquire_semaphore(bank, offset)) {

			dev_err(pctl->dev, "pin %d not available.\n", pin);

			return -EINVAL;

		}

	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

		dev_err(pctl->dev, "pin %d not available.\n", offset);

		return -EACCES;

	}



	return pinctrl_gpio_request(chip, offset);
@@ -1040,7 +1038,9 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 
static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)

{

	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);

	unsigned int offset = stm32_gpio_pin(gpio);

	struct pinctrl_gpio_range *range;

	struct stm32_gpio_bank *bank;



	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);

	if (!range) {
@@ -1048,11 +1048,20 @@ static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) 
		return -EINVAL;

	}



	if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {

	if (!gpiochip_line_is_valid(range->gc, offset)) {

		dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);

		return -EACCES;

	}



	bank = gpiochip_get_data(range->gc);

	if (!bank)

		return -ENODEV;



	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

		dev_err(pctl->dev, "pin %d not available.\n", offset);

		return -EACCES;

	}



	return 0;

}
@@ -1394,6 +1403,11 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 
		return -EACCES;

	}



	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

		dev_err(pctl->dev, "pin %d not available.\n", offset);

		return -EACCES;

	}



	switch (param) {

	case PIN_CONFIG_DRIVE_PUSH_PULL:

		ret = stm32_pconf_set_driving(bank, offset, 0);
@@ -2014,16 +2028,21 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 
	if (!range)

		return 0;



	bank = gpiochip_get_data(range->gc);



	if (!gpiochip_line_is_valid(range->gc, offset))

		return 0;



	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {

		dev_err(pctl->dev, "pin %d not available.\n", offset);

		return -EACCES;

	}



	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);



	if (!desc || (!pin_is_irq && !desc->gpio_owner))

		return 0;



	bank = gpiochip_get_data(range->gc);



	mode = bank->pin_backup[offset].mode;

	ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt);

	if (ret)