Commit 796b6df0 authored by Chaitanya Kumar Borah's avatar Chaitanya Kumar Borah Committed by Animesh Manna
Browse files

drm/i915/dsb: add intel_dsb_gosub_finish() 



A DSB buffer which will be used for GOSUB execution does not need
the DEWAKE mechanism but still need to be 64 bit aligned. Add helper
to finish preparation of a dsb buffer to be executed with GOSUB
instruction.

v2: Add a cacheline of noops at the end of GOSUB buffer (Ville)

Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-6-chaitanya.kumar.borah@intel.com
parent 2c41d62f

drivers/gpu/drm/i915/display/intel_dsb.c

+13 −0
Original line number Diff line number Diff line
@@ -606,6 +606,19 @@ void intel_dsb_gosub(struct intel_dsb *dsb, 
	intel_dsb_align_tail(dsb);

}



void intel_dsb_gosub_finish(struct intel_dsb *dsb)

{

	intel_dsb_align_tail(dsb);



	/*

	 * "All subroutines called by the GOSUB instruction

	 *  must end with a cacheline of NOPs"

	 */

	intel_dsb_noop(dsb, 8);



	intel_dsb_buffer_flush_map(&dsb->dsb_buf);

}



void intel_dsb_finish(struct intel_dsb *dsb)

{

	struct intel_crtc *crtc = dsb->crtc;

drivers/gpu/drm/i915/display/intel_dsb.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, 
				    enum intel_dsb_id dsb_id,

				    unsigned int max_cmds);

void intel_dsb_finish(struct intel_dsb *dsb);

void intel_dsb_gosub_finish(struct intel_dsb *dsb);

void intel_dsb_cleanup(struct intel_dsb *dsb);

void intel_dsb_reg_write(struct intel_dsb *dsb,

			 i915_reg_t reg, u32 val);