Commit 79819d9a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/uq: make MES UQ setup generic 



Now that all of the IP specific code has been moved into
the IP specific functions, we can make this code generic.

V2: Fixed build errors and porting logics (Shashank)

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b965c5d8

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ amdgpu-y += \ 
	mes_v12_0.o \



# add GFX userqueue support

amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_v11_0_userqueue.o

amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_userqueue.o



# add UVD block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+5 −5
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
#include "gfx_v11_0_3.h"

#include "nbio_v4_3.h"

#include "mes_v11_0.h"

#include "mes_v11_0_userqueue.h"

#include "mes_userqueue.h"

#include "amdgpu_userq_fence.h"



#define GFX11_NUM_GFX_RINGS		1
@@ -1623,8 +1623,8 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;

#endif

		break;

	case IP_VERSION(11, 0, 1):
@@ -1640,8 +1640,8 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

#ifdef CONFIG_DRM_AMD_USERQ_GFX

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;

#endif

		break;

	default:

drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c→drivers/gpu/drm/amd/amdgpu/mes_userqueue.c

+40 −37
Original line number Diff line number Diff line
@@ -23,14 +23,15 @@ 
 */

#include "amdgpu.h"

#include "amdgpu_gfx.h"

#include "mes_v11_0_userqueue.h"

#include "mes_userqueue.h"

#include "amdgpu_userq_fence.h"

#include "v11_structs.h"



#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE

#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE



static int

mes_v11_0_map_gtt_bo_to_gart(struct amdgpu_bo *bo)

mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo)

{

	int ret;
@@ -58,7 +59,7 @@ mes_v11_0_map_gtt_bo_to_gart(struct amdgpu_bo *bo) 
}



static int

mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,

mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,

			      struct amdgpu_usermode_queue *queue,

			      uint64_t wptr)

{
@@ -86,7 +87,7 @@ mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, 
		return -EINVAL;

	}



	ret = mes_v11_0_map_gtt_bo_to_gart(wptr_obj->obj);

	ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj);

	if (ret) {

		DRM_ERROR("Failed to map wptr bo to GART\n");

		return ret;
@@ -96,7 +97,7 @@ mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, 
	return 0;

}



static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr,

static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr,

			 struct amdgpu_usermode_queue *queue,

			 struct amdgpu_mqd_prop *userq_props)

{
@@ -142,7 +143,7 @@ static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr, 
	return 0;

}



static void mes_v11_0_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,

static void mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,

			    struct amdgpu_usermode_queue *queue)

{

	struct amdgpu_device *adev = uq_mgr->adev;
@@ -162,7 +163,7 @@ static void mes_v11_0_userq_unmap(struct amdgpu_userq_mgr *uq_mgr, 
	queue->queue_active = false;

}



static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,

static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,

				      struct amdgpu_usermode_queue *queue,

				      struct drm_amdgpu_userq_in *mqd_user)

{
@@ -184,7 +185,7 @@ static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 
	return 0;

}



static void mes_v11_0_userq_set_fence_space(struct amdgpu_usermode_queue *queue)

static void mes_userq_set_fence_space(struct amdgpu_usermode_queue *queue)

{

	struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
@@ -192,7 +193,7 @@ static void mes_v11_0_userq_set_fence_space(struct amdgpu_usermode_queue *queue) 
	mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);

}



static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,

static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,

				struct drm_amdgpu_userq_in *args_in,

				struct amdgpu_usermode_queue *queue)

{
@@ -257,14 +258,15 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 


		if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) {

			DRM_ERROR("Invalid GFX MQD\n");

			return -EINVAL;

			r = -EINVAL;

			goto free_mqd;

		}



		mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);

		if (IS_ERR(mqd_gfx_v11)) {

			DRM_ERROR("Failed to read user MQD\n");

			amdgpu_userqueue_destroy_object(uq_mgr, ctx);

			return -ENOMEM;

			r = -ENOMEM;

			goto free_mqd;

		}



		userq_props->shadow_addr = mqd_gfx_v11->shadow_va;
@@ -275,14 +277,15 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 


		if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) {

			DRM_ERROR("Invalid SDMA MQD\n");

			return -EINVAL;

			r = -EINVAL;

			goto free_mqd;

		}



		mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);

		if (IS_ERR(mqd_sdma_v11)) {

			DRM_ERROR("Failed to read sdma user MQD\n");

			amdgpu_userqueue_destroy_object(uq_mgr, ctx);

			return -ENOMEM;

			r = -ENOMEM;

			goto free_mqd;

		}



		userq_props->csa_addr = mqd_sdma_v11->csa_va;
@@ -298,23 +301,23 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 
	}



	/* Create BO for FW operations */

	r = mes_v11_0_userq_create_ctx_space(uq_mgr, queue, mqd_user);

	r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user);

	if (r) {

		DRM_ERROR("Failed to allocate BO for userqueue (%d)", r);

		goto free_mqd;

	}



	mes_v11_0_userq_set_fence_space(queue);

	mes_userq_set_fence_space(queue);



	/* FW expects WPTR BOs to be mapped into GART */

	r = mes_v11_0_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr);

	r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr);

	if (r) {

		DRM_ERROR("Failed to create WPTR mapping\n");

		goto free_ctx;

	}



	/* Map userqueue into FW using MES */

	r = mes_v11_0_userq_map(uq_mgr, queue, userq_props);

	r = mes_userq_map(uq_mgr, queue, userq_props);

	if (r) {

		DRM_ERROR("Failed to init MQD\n");

		goto free_ctx;
@@ -335,29 +338,29 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 
}



static void

mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,

mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,

			    struct amdgpu_usermode_queue *queue)

{

	if (queue->queue_active)

		mes_v11_0_userq_unmap(uq_mgr, queue);

		mes_userq_unmap(uq_mgr, queue);



	amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj);

	kfree(queue->userq_prop);

	amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd);

}



static int mes_v11_0_userq_suspend(struct amdgpu_userq_mgr *uq_mgr,

static int mes_userq_suspend(struct amdgpu_userq_mgr *uq_mgr,

				   struct amdgpu_usermode_queue *queue)

{

	if (queue->queue_active) {

		mes_v11_0_userq_unmap(uq_mgr, queue);

		mes_userq_unmap(uq_mgr, queue);

		queue->queue_active = false;

	}



	return 0;

}



static int mes_v11_0_userq_resume(struct amdgpu_userq_mgr *uq_mgr,

static int mes_userq_resume(struct amdgpu_userq_mgr *uq_mgr,

				  struct amdgpu_usermode_queue *queue)

{

	int ret;
@@ -365,7 +368,7 @@ static int mes_v11_0_userq_resume(struct amdgpu_userq_mgr *uq_mgr, 
	if (queue->queue_active)

		return 0;



	ret = mes_v11_0_userq_map(uq_mgr, queue, queue->userq_prop);

	ret = mes_userq_map(uq_mgr, queue, queue->userq_prop);

	if (ret) {

		DRM_ERROR("Failed to resume queue\n");

		return ret;
@@ -375,9 +378,9 @@ static int mes_v11_0_userq_resume(struct amdgpu_userq_mgr *uq_mgr, 
	return 0;

}



const struct amdgpu_userq_funcs userq_mes_v11_0_funcs = {

	.mqd_create = mes_v11_0_userq_mqd_create,

	.mqd_destroy = mes_v11_0_userq_mqd_destroy,

	.suspend = mes_v11_0_userq_suspend,

	.resume = mes_v11_0_userq_resume,

const struct amdgpu_userq_funcs userq_mes_funcs = {

	.mqd_create = mes_userq_mqd_create,

	.mqd_destroy = mes_userq_mqd_destroy,

	.suspend = mes_userq_suspend,

	.resume = mes_userq_resume,

};

drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h→drivers/gpu/drm/amd/amdgpu/mes_userqueue.h

+3 −3
Original line number Diff line number Diff line
@@ -22,9 +22,9 @@ 
 *

 */



#ifndef MES_V11_0_USERQ_H

#define MES_V11_0_USERQ_H

#ifndef MES_USERQ_H

#define MES_USERQ_H

#include "amdgpu_userqueue.h"



extern const struct amdgpu_userq_funcs userq_mes_v11_0_funcs;

extern const struct amdgpu_userq_funcs userq_mes_funcs;

#endif

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

+2 −2
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
#include "sdma_common.h"

#include "sdma_v6_0.h"

#include "v11_structs.h"

#include "mes_v11_0_userqueue.h"

#include "mes_userqueue.h"



MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");

MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
@@ -1381,7 +1381,7 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 
		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");



#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

	adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_v11_0_funcs;

	adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;

#endif

	r = amdgpu_sdma_sysfs_reset_mask_init(adev);

	if (r)