Commit 79cf71c0 authored by Shawn Lin's avatar Shawn Lin Committed by Ulf Hansson
Browse files

mmc: sdhci-of-dwcmshc: reduce CIT for better performance 



CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
hardware queue, and CMD13 can only query one slot at a time for data
transmission, which cannot be processed in parallel. Modifying the
CMD13 query interval can increase the query frequency and improve
random write performance.

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent c7ce6453

drivers/mmc/host/cqhci.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
/* send status config 1 */

#define CQHCI_SSC1			0x40

#define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)

#define CQHCI_SSC1_CIT_MASK		GENMASK(15, 0)



/* send status config 2 */

#define CQHCI_SSC2			0x44

drivers/mmc/host/sdhci-of-dwcmshc.c

+5 −0
Original line number Diff line number Diff line
@@ -644,6 +644,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc) 
	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);

	u32 reg;



	/* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */

	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);

	reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;

	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);



	reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);

	reg |= CQHCI_ENABLE;

	sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);