Commit 79d92dba authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Correct display clocks update block sequence 



[WHY&HOW]
At the time of block sequence construction, the exact reference DPP/DISP clock is
not yet known, so the clock should be passed by reference to the DTO programming
function.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9716bae1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

+270 −307

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

+2 −6
Original line number Diff line number Diff line
@@ -54,18 +54,17 @@ union dcn401_clk_mgr_block_sequence_params { 
	struct {

		/* inputs */

		struct dc_state *context;

		int dppclk_khz;

		int *ref_dppclk_khz;

		bool safe_to_lower;

	} update_dppclk_dto_params;

	struct {

		/* inputs */

		struct dc_state *context;

		int ref_dtbclk_khz;

		int *ref_dtbclk_khz;

	} update_dtbclk_dto_params;

	struct {

		/* inputs */

		struct dc_state *context;

		int ref_dtbclk_khz;

	} update_dentist_params;

	struct {

		/* inputs */
@@ -108,9 +107,6 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base); 
struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,

		struct dccg *dccg);



void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

		struct dc_state *context, bool safe_to_lower, int dppclk_khz);



void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);



#endif /* __DCN401_CLK_MGR_H_ */