Commit 7a03ef9f authored by Ovidiu Panait's avatar Ovidiu Panait Committed by Geert Uytterhoeven
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clk: renesas: r9a09g057: Add clock and reset entries for RTC 



Add module clock and reset entries for the RTC module on the Renesas RZ/V2H
(R9A09G057) SoC.

Signed-off-by: default avatarOvidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251021080705.18116-2-ovidiu.panait.rb@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a7231aaf

drivers/clk/renesas/r9a09g057-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -241,6 +241,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,

						BUS_MSTOP(3, BIT(11) | BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,
@@ -415,6 +417,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(7, 9, 3, 10),		/* RTC_0_RST_RTC */

	DEF_RST(7, 10, 3, 11),		/* RTC_0_RST_RTC_V */

	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */

	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */

	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */