Commit 7a0df1f9 authored by Peng Fan's avatar Peng Fan Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: k3-j721e: correct cache-sets info 



A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

So correct the cache-sets info.

Fixes: 2d87061e ("arm64: dts: ti: Add Support for J721E SoC")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com
parent fa55b7dc

arch/arm64/boot/dts/ti/k3-j721e.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ cpu0: cpu@0 { 
			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_0>;

		};
@@ -78,7 +78,7 @@ cpu1: cpu@1 { 
			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_0>;

		};

	};