Loading arch/sparc64/mm/init.c +28 −22 Original line number Diff line number Diff line Loading @@ -188,8 +188,9 @@ atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); #endif #endif __inline__ void flush_dcache_page_impl(struct page *page) inline void flush_dcache_page_impl(struct page *page) { BUG_ON(tlb_type == hypervisor); #ifdef CONFIG_DEBUG_DCFLUSH atomic_inc(&dcpage_flushes); #endif Loading Loading @@ -279,11 +280,12 @@ unsigned long _PAGE_SZBITS __read_mostly; void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) { struct mm_struct *mm; struct page *page; unsigned long pfn; if (tlb_type != hypervisor) { unsigned long pfn = pte_pfn(pte); unsigned long pg_flags; struct page *page; pfn = pte_pfn(pte); if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) && ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { Loading @@ -303,6 +305,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p put_cpu(); } } mm = vma->vm_mm; if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) { Loading @@ -321,6 +324,9 @@ void flush_dcache_page(struct page *page) struct address_space *mapping; int this_cpu; if (tlb_type == hypervisor) return; /* Do not bother with the expensive D-cache flush if it * is merely the zero page. The 'bigcore' testcase in GDB * causes this case to run millions of times. Loading arch/sparc64/mm/tlb.c +2 −1 Original line number Diff line number Diff line Loading @@ -49,7 +49,8 @@ void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t if (pte_exec(orig)) vaddr |= 0x1UL; if (pte_dirty(orig)) { if (tlb_type != hypervisor && pte_dirty(orig)) { unsigned long paddr, pfn = pte_pfn(orig); struct address_space *mapping; struct page *page; Loading Loading
arch/sparc64/mm/init.c +28 −22 Original line number Diff line number Diff line Loading @@ -188,8 +188,9 @@ atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); #endif #endif __inline__ void flush_dcache_page_impl(struct page *page) inline void flush_dcache_page_impl(struct page *page) { BUG_ON(tlb_type == hypervisor); #ifdef CONFIG_DEBUG_DCFLUSH atomic_inc(&dcpage_flushes); #endif Loading Loading @@ -279,11 +280,12 @@ unsigned long _PAGE_SZBITS __read_mostly; void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) { struct mm_struct *mm; struct page *page; unsigned long pfn; if (tlb_type != hypervisor) { unsigned long pfn = pte_pfn(pte); unsigned long pg_flags; struct page *page; pfn = pte_pfn(pte); if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) && ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { Loading @@ -303,6 +305,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p put_cpu(); } } mm = vma->vm_mm; if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) { Loading @@ -321,6 +324,9 @@ void flush_dcache_page(struct page *page) struct address_space *mapping; int this_cpu; if (tlb_type == hypervisor) return; /* Do not bother with the expensive D-cache flush if it * is merely the zero page. The 'bigcore' testcase in GDB * causes this case to run millions of times. Loading
arch/sparc64/mm/tlb.c +2 −1 Original line number Diff line number Diff line Loading @@ -49,7 +49,8 @@ void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t if (pte_exec(orig)) vaddr |= 0x1UL; if (pte_dirty(orig)) { if (tlb_type != hypervisor && pte_dirty(orig)) { unsigned long paddr, pfn = pte_pfn(orig); struct address_space *mapping; struct page *page; Loading