Commit 7a9536e7 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'fixes-for-mv88e6xxx-mainly-6320-family' 

Marek Behún says:

====================
Fixes for mv88e6xxx (mainly 6320 family)

v1: https://patchwork.kernel.org/project/netdevbpf/cover/20250313134146.27087-1-kabel@kernel.org/
====================

Link: https://patch.msgid.link/20250317173250.28780-1-kabel@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 7011ba33 1ebc8e1e

drivers/net/dsa/mv88e6xxx/chip.c

+36 −8
Original line number Diff line number Diff line
@@ -3674,6 +3674,21 @@ static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 
	return mv88e6xxx_g1_stats_clear(chip);

}



static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip)

{

	u16 dummy;

	int err;



	/* Workaround for erratum

	 *   3.3 RGMII timing may be out of spec when transmit delay is enabled

	 */

	err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000);

	if (err)

		return err;



	return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy);

}



/* Check if the errata has already been applied. */

static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)

{
@@ -5130,6 +5145,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 


static const struct mv88e6xxx_ops mv88e6320_ops = {

	/* MV88E6XXX_FAMILY_6320 */

	.setup_errata = mv88e6320_setup_errata,

	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,

	.ip_pri_map = mv88e6085_g1_ip_pri_map,

	.irl_init_all = mv88e6352_g2_irl_init_all,
@@ -5145,6 +5161,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 
	.port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,

	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
@@ -5169,8 +5186,10 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 
	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,

	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,

	.reset = mv88e6352_g1_reset,

	.vtu_getnext = mv88e6185_g1_vtu_getnext,

	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,

	.vtu_getnext = mv88e6352_g1_vtu_getnext,

	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,

	.stu_getnext = mv88e6352_g1_stu_getnext,

	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,

	.gpio_ops = &mv88e6352_gpio_ops,

	.avb_ops = &mv88e6352_avb_ops,

	.ptp_ops = &mv88e6352_ptp_ops,
@@ -5179,6 +5198,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 


static const struct mv88e6xxx_ops mv88e6321_ops = {

	/* MV88E6XXX_FAMILY_6320 */

	.setup_errata = mv88e6320_setup_errata,

	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,

	.ip_pri_map = mv88e6085_g1_ip_pri_map,

	.irl_init_all = mv88e6352_g2_irl_init_all,
@@ -5194,6 +5214,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 
	.port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,

	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_tag_remap = mv88e6095_port_tag_remap,

	.port_set_policy = mv88e6352_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
@@ -5217,8 +5238,10 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 
	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,

	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,

	.reset = mv88e6352_g1_reset,

	.vtu_getnext = mv88e6185_g1_vtu_getnext,

	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,

	.vtu_getnext = mv88e6352_g1_vtu_getnext,

	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,

	.stu_getnext = mv88e6352_g1_stu_getnext,

	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,

	.gpio_ops = &mv88e6352_gpio_ops,

	.avb_ops = &mv88e6352_avb_ops,

	.ptp_ops = &mv88e6352_ptp_ops,
@@ -5818,7 +5841,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.global1_addr = 0x1b,

		.global2_addr = 0x1c,

		.age_time_coeff = 3750,

		.atu_move_port_mask = 0x1f,

		.atu_move_port_mask = 0xf,

		.g1_irqs = 9,

		.g2_irqs = 10,

		.stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
@@ -6236,9 +6259,11 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.num_databases = 4096,

		.num_macs = 8192,

		.num_ports = 7,

		.num_internal_phys = 5,

		.num_internal_phys = 2,

		.internal_phys_offset = 3,

		.num_gpio = 15,

		.max_vid = 4095,

		.max_sid = 63,

		.port_base_addr = 0x10,

		.phy_base_addr = 0x0,

		.global1_addr = 0x1b,
@@ -6262,9 +6287,11 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.num_databases = 4096,

		.num_macs = 8192,

		.num_ports = 7,

		.num_internal_phys = 5,

		.num_internal_phys = 2,

		.internal_phys_offset = 3,

		.num_gpio = 15,

		.max_vid = 4095,

		.max_sid = 63,

		.port_base_addr = 0x10,

		.phy_base_addr = 0x0,

		.global1_addr = 0x1b,
@@ -6274,6 +6301,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.g2_irqs = 10,

		.stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,

		.atu_move_port_mask = 0xf,

		.pvt = true,

		.multi_chip = true,

		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,

		.ptp_support = true,
@@ -6296,7 +6324,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.global1_addr = 0x1b,

		.global2_addr = 0x1c,

		.age_time_coeff = 3750,

		.atu_move_port_mask = 0x1f,

		.atu_move_port_mask = 0xf,

		.g1_irqs = 9,

		.g2_irqs = 10,

		.stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1,