Commit 7b26feb4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull SoC fixes from Arnd Bergmann:
 "The main changes are once more for the NXP i.MX platform, addressing
  multiple regressions in recent devicetree updates for the i.MX8MM and
  i.MX6ULL SoCs, a PCIe fix for i.MX9 and a MAINTAINERS file update to
  disambiguate NXP i.MX SoCs from Sony IMX image sensors.

  The stm32 platform devicetree files get some compatibility fixes for
  the interrupt controller node.

  Another compatibility fix is done for the Arm Morello platform's cache
  controller node.

  The code changes are all for firmware drivers, fixing kernel-side bugs
  on the Arm FF-A and SCMI drivers"

* tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp23 SoCs
  arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCs
  arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp21 SoCs
  arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCs
  arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp25 SoCs
  arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCs
  arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2
  MAINTAINERS: add exclude for dt-bindings to imx entry
  ARM: dts: opos6ul: add ksz8081 phy properties
  arm64: dts: imx95: Correct the range of PCIe app-reg region
  arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI
  arm64: dts: morello: Fix-up cache nodes
  firmware: arm_ffa: Skip Rx buffer ownership release if not acquired
  firmware: arm_scmi: Fix timeout checks on polling path
  firmware: arm_scmi: Balance device refcount when destroying devices
parents 92a09c47 2ef5c66c

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -2519,6 +2519,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git 
F:	arch/arm/boot/dts/nxp/imx/

F:	arch/arm/boot/dts/nxp/mxs/

F:	arch/arm64/boot/dts/freescale/

X:	Documentation/devicetree/bindings/media/i2c/

X:	arch/arm64/boot/dts/freescale/fsl-*

X:	arch/arm64/boot/dts/freescale/qoriq-*

X:	drivers/media/i2c/

arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ ethphy1: ethernet-phy@1 { 
			reg = <1>;

			interrupt-parent = <&gpio4>;

			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;

			micrel,led-mode = <1>;

			clocks = <&clks IMX6UL_CLK_ENET_REF>;

			clock-names = "rmii-ref";

			status = "okay";

		};

	};

arch/arm64/boot/dts/arm/morello.dtsi

+11 −11
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ cpu0: cpu@0 { 
			next-level-cache = <&l2_0>;

			clocks = <&scmi_dvfs 0>;



			l2_0: l2-cache-0 {

			l2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				/* 8 ways set associative */
@@ -53,13 +53,6 @@ l2_0: l2-cache-0 { 
				cache-sets = <2048>;

				cache-unified;

				next-level-cache = <&l3_0>;



				l3_0: l3-cache {

					compatible = "cache";

					cache-level = <3>;

					cache-size = <0x100000>;

					cache-unified;

				};

			};

		};
@@ -78,7 +71,7 @@ cpu1: cpu@100 { 
			next-level-cache = <&l2_1>;

			clocks = <&scmi_dvfs 0>;



			l2_1: l2-cache-1 {

			l2_1: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				/* 8 ways set associative */
@@ -105,7 +98,7 @@ cpu2: cpu@10000 { 
			next-level-cache = <&l2_2>;

			clocks = <&scmi_dvfs 1>;



			l2_2: l2-cache-2 {

			l2_2: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				/* 8 ways set associative */
@@ -132,7 +125,7 @@ cpu3: cpu@10100 { 
			next-level-cache = <&l2_3>;

			clocks = <&scmi_dvfs 1>;



			l2_3: l2-cache-3 {

			l2_3: l2-cache {

				compatible = "cache";

				cache-level = <2>;

				/* 8 ways set associative */
@@ -143,6 +136,13 @@ l2_3: l2-cache-3 { 
				next-level-cache = <&l3_0>;

			};

		};



		l3_0: l3-cache {

			compatible = "cache";

			cache-level = <3>;

			cache-size = <0x100000>;

			cache-unified;

		};

	};



	firmware {

arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

+20 −5
Original line number Diff line number Diff line
@@ -144,6 +144,19 @@ reg_usdhc2_vmmc: regulator-usdhc2 { 
		startup-delay-us = <20000>;

	};



	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {

		compatible = "regulator-gpio";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usdhc2_vsel>;

		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

		regulator-max-microvolt = <3300000>;

		regulator-min-microvolt = <1800000>;

		states = <1800000 0x1>,

			 <3300000 0x0>;

		regulator-name = "PMIC_USDHC_VSELECT";

		vin-supply = <&reg_nvcc_sd>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -269,7 +282,7 @@ &gpio1 { 
			  "SODIMM_19",

			  "",

			  "",

			  "",

			  "PMIC_USDHC_VSELECT",

			  "",

			  "",

			  "",
@@ -785,6 +798,7 @@ &usdhc2 { 
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;

	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	vqmmc-supply = <&reg_usdhc2_vqmmc>;

};



&wdog1 {
@@ -1206,13 +1220,17 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 
			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */

	};



	pinctrl_usdhc2_vsel: usdhc2vselgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x10>; /* PMIC_USDHC_VSELECT */

	};



	/*

	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the

	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.

	 */

	pinctrl_usdhc2: usdhc2grp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90>,	/* SODIMM 78 */

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90>,	/* SODIMM 74 */

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90>,	/* SODIMM 80 */
@@ -1223,7 +1241,6 @@ pinctrl_usdhc2: usdhc2grp { 


	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94>,
@@ -1234,7 +1251,6 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 


	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96>,
@@ -1246,7 +1262,6 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 
	/* Avoid backfeeding with removed card power */

	pinctrl_usdhc2_sleep: usdhc2slpgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,

arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -24,6 +24,20 @@ &clk { 
	fsl,operating-mode = "nominal";

};



&gpu2d {

	assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;

	assigned-clock-rates = <800000000>;

};



&gpu3d {

	assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,

			  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

				 <&clk IMX8MP_SYS_PLL1_800M>;

	assigned-clock-rates = <800000000>, <800000000>;

};



&pgc_hdmimix {

	assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,

			  <&clk IMX8MP_CLK_HDMI_APB>;
@@ -46,6 +60,18 @@ &pgc_gpumix { 
	assigned-clock-rates = <600000000>, <300000000>;

};



&pgc_mlmix {

	assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,

			  <&clk IMX8MP_CLK_ML_AXI>,

			  <&clk IMX8MP_CLK_ML_AHB>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

				 <&clk IMX8MP_SYS_PLL1_800M>,

				 <&clk IMX8MP_SYS_PLL1_800M>;

	assigned-clock-rates = <800000000>,

			       <800000000>,

			       <300000000>;

};



&media_blk_ctrl {

	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,

			  <&clk IMX8MP_CLK_MEDIA_APB>,