Commit 7b775d36 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES() 



As done previously for pll, also convert users of _PHY3() to
_PICK_EVEN_2RANGES(). Size comparison of i915.o:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.old
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.new

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230120193457.3295977-5-lucas.demarchi@intel.com
parent 680d0c79

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

+0 −3
Original line number Diff line number Diff line
@@ -29,11 +29,8 @@ 
#define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))

#define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))



#define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)



#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))

#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))

#define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))



/*

 * Device info offset array based helpers for groups of registers with unevenly

drivers/gpu/drm/i915/i915_reg.h

+9 −7
Original line number Diff line number Diff line
@@ -541,9 +541,10 @@ 
#define _BXT_PHY0_BASE			0x6C000

#define _BXT_PHY1_BASE			0x162000

#define _BXT_PHY2_BASE			0x163000

#define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \

						     _BXT_PHY1_BASE, \

						     _BXT_PHY2_BASE)

#define BXT_PHY_BASE(phy)							\

	 _PICK_EVEN_2RANGES(phy, 1,						\

			    _BXT_PHY0_BASE, _BXT_PHY0_BASE,			\

			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)



#define _BXT_PHY(phy, reg)						\

	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
@@ -566,13 +567,14 @@ 
#define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \

							 _BXT_PHY_CTL_DDI_B)



#define _PHY_CTL_FAMILY_EDP		0x64C80

#define _PHY_CTL_FAMILY_DDI		0x64C90

#define _PHY_CTL_FAMILY_EDP		0x64C80

#define _PHY_CTL_FAMILY_DDI_C		0x64CA0

#define   COMMON_RESET_DIS		(1 << 31)

#define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \

							  _PHY_CTL_FAMILY_EDP, \

							  _PHY_CTL_FAMILY_DDI_C)

#define BXT_PHY_CTL_FAMILY(phy)							\

	 _MMIO(_PICK_EVEN_2RANGES(phy, 1,					\

				  _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI,	\

				  _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))



/* BXT PHY PLL registers */

#define _PORT_PLL_A			0x46074