Commit 7b776229 authored by Dominik Haller's avatar Dominik Haller Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-phycore-som: Add overlay for rproc 



Adds a devicetree overlay containing reserved memory regions used
for intercore communication between A53 and M4 cores.

Signed-off-by: default avatarDominik Haller <d.haller@phytec.de>
Signed-off-by: default avatarAndrej Picej <andrej.picej@norik.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 481bc9d5

arch/arm64/boot/dts/freescale/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -125,9 +125,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb 


imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo

imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo

imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo



dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb



dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb

arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso

0 → 100644
+58 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2025 PHYTEC Messtechnik GmbH

 * Author: Dominik Haller <d.haller@phytec.de>

 */



/dts-v1/;

/plugin/;



#include <dt-bindings/clock/imx8mm-clock.h>



&{/} {

	#address-cells = <2>;

	#size-cells = <2>;



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		m4_reserved: m4@80000000 {

			reg = <0 0x80000000 0 0x1000000>;

			no-map;

		};



		vdev0vring0: vdev0vring0@b8000000 {

			reg = <0 0xb8000000 0 0x8000>;

			no-map;

		};



		vdev0vring1: vdev0vring1@b8008000 {

			reg = <0 0xb8008000 0 0x8000>;

			no-map;

		};



		rsc_table: rsc_table@b80ff000 {

			reg = <0 0xb80ff000 0 0x1000>;

			no-map;

		};



		vdevbuffer: vdevbuffer@b8400000 {

			compatible = "shared-dma-pool";

			reg = <0 0xb8400000 0 0x100000>;

			no-map;

		};

	};



	core-m4 {

		compatible = "fsl,imx8mm-cm4";

		clocks = <&clk IMX8MM_CLK_M4_DIV>;

		mboxes = <&mu 0 1

			&mu 1 1

			&mu 3 1>;

		mbox-names = "tx", "rx", "rxdb";

		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;

		syscon = <&src>;

	};

};