Commit 7b82df33 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'arm/fixes' into soc/late2

* arm/fixes:
  arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
  reset: amlogic: t7: Fix null reset ops
  arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
  arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
  dt-bindings: arm64: add Marvell 7k COMe boards
parents 8242c709 3e244404
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+11 −0
Original line number Diff line number Diff line
@@ -21,6 +21,17 @@ properties:
          - const: marvell,armada-ap806-dual
          - const: marvell,armada-ap806

      - description:
          Falcon (DB-98CX85x0) Development board COM Express Carrier plus
          Armada 7020 SoC COM Express CPU module
        items:
          - const: marvell,armada7020-falcon-carrier
          - const: marvell,db-falcon-carrier
          - const: marvell,armada7020-cpu-module
          - const: marvell,armada7020
          - const: marvell,armada-ap806-dual
          - const: marvell,armada-ap806

      - description: Armada 7040 SoC
        items:
          - enum:
+2 −2
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ pmic@25 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
@@ -194,7 +194,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3

	pinctrl_pmic: emtop-pmic-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3			0x41
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3			0x141
		>;
	};

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x94>;
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x1d4>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+1 −1
Original line number Diff line number Diff line
@@ -283,7 +283,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x84>;
		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x1c4>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+1 −1
Original line number Diff line number Diff line
@@ -903,7 +903,7 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x41

	pinctrl_pmic: aristainetos3-pmic-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x1c0
		>;
	};

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