Commit 7beee6e9 authored by Cruise Hung's avatar Cruise Hung Committed by Alex Deucher
Browse files

drm/amd/display: Add new DP tunnel bandwidth validation 



[Why & How]
Add new function for DP tunnel bandwidth validation.
It uses the estimated BW and allocated BW to validate the timings.

Reviewed-by: default avatarPeiChen Huang <peichen.huang@amd.com>
Reviewed-by: default avatarMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: default avatarCruise Hung <Cruise.Hung@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0c5f7371

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

+2 −0
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ char *dc_status_to_str(enum dc_status status) 
		return "Insufficient DP link bandwidth";

	case DC_FAIL_HW_CURSOR_SUPPORT:

		return "HW Cursor not supported";

	case DC_FAIL_DP_TUNNEL_BW_VALIDATE:

		return "Fail DP Tunnel BW validation";

	case DC_ERROR_UNEXPECTED:

		return "Unexpected error";

	}

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

+6 −0
Original line number Diff line number Diff line
@@ -519,3 +519,9 @@ bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *strea 
{

	return dc->link_srv->validate_dpia_bandwidth(streams, count);

}



enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

{

	return dc->link_srv->validate_dp_tunnel_bandwidth(dc, new_ctx);

}

drivers/gpu/drm/amd/display/dc/dc.h

+12 −2
Original line number Diff line number Diff line
@@ -68,10 +68,12 @@ struct dmub_notification; 
#define MAX_STREAMS 6

#define MIN_VIEWPORT_SIZE 12

#define MAX_NUM_EDP 2

#define MAX_HOST_ROUTERS_NUM 3

#define MAX_DPIA_PER_HOST_ROUTER 2

#define MAX_SUPPORTED_FORMATS 7



#define MAX_HOST_ROUTERS_NUM 3

#define MAX_DPIA_PER_HOST_ROUTER 3

#define MAX_DPIA_NUM  (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER)



/* Display Core Interfaces */

struct dc_versions {

	const char *dc_ver;
@@ -2427,6 +2429,14 @@ void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 
bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,

		const unsigned int count);



/*

 * Calculates the DP tunneling bandwidth required for the stream timing

 * and aggregates the stream bandwidth for the respective DP tunneling link

 *

 * return: dc_status

 */

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);



/* Sink Interfaces - A sink corresponds to a display output device */



struct dc_container_id {

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+15 −0
Original line number Diff line number Diff line
@@ -162,6 +162,11 @@ struct dc_link_settings { 
struct dc_tunnel_settings {

	bool should_enable_dp_tunneling;

	bool should_use_dp_bw_allocation;

	uint8_t cm_id;

	uint8_t group_id;

	uint32_t bw_granularity;

	uint32_t estimated_bw;

	uint32_t allocated_bw;

};



union dc_dp_ffe_preset {
@@ -957,11 +962,21 @@ union usb4_driver_bw_cap { 
	uint8_t raw;

};



/* DPCD[0xE0021] DP_IN_ADAPTER_TUNNEL_INFORMATION register. */

union dpia_tunnel_info {

	struct {

		uint8_t group_id :3;

		uint8_t rsvd :5;

	} bits;

	uint8_t raw;

};



/* DP Tunneling over USB4 */

struct dpcd_usb4_dp_tunneling_info {

	union dp_tun_cap_support dp_tun_cap;

	union dpia_info dpia_info;

	union usb4_driver_bw_cap driver_bw_cap;

	union dpia_tunnel_info dpia_tunnel_info;

	uint8_t usb4_driver_id;

	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];

};

drivers/gpu/drm/amd/display/dc/dc_types.h

+7 −0
Original line number Diff line number Diff line
@@ -1378,4 +1378,11 @@ enum dc_validate_mode { 
	/* validate the mode and get the max state (voltage level) */

	DC_VALIDATE_MODE_AND_STATE_INDEX = 2,

};



struct dc_validation_dpia_set {

	const struct dc_link *link;

	const struct dc_tunnel_settings *tunnel_settings;

	uint32_t required_bw;

};



#endif /* DC_TYPES_H_ */