Commit 7bf71532 authored by Brian Masney's avatar Brian Masney
Browse files

clk: versaclock5: convert from round_rate() to determine_rate() 



The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Reviewed-by: default avatarLuca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: default avatarBrian Masney <bmasney@redhat.com>
parent 7a19c341

drivers/clk/clk-versaclock5.c

+40 −31
Original line number Diff line number Diff line
@@ -304,11 +304,11 @@ static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, 
	return parent_rate;

}



static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,

			       unsigned long *parent_rate)

static int vc5_dbl_determine_rate(struct clk_hw *hw,

				  struct clk_rate_request *req)

{

	if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))

		return rate;

	if ((req->best_parent_rate == req->rate) || ((req->best_parent_rate * 2) == req->rate))

		return 0;

	else

		return -EINVAL;

}
@@ -332,7 +332,7 @@ static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops vc5_dbl_ops = {

	.recalc_rate	= vc5_dbl_recalc_rate,

	.round_rate	= vc5_dbl_round_rate,

	.determine_rate = vc5_dbl_determine_rate,

	.set_rate	= vc5_dbl_set_rate,

};
@@ -363,24 +363,29 @@ static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, 
		return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);

}



static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,

			       unsigned long *parent_rate)

static int vc5_pfd_determine_rate(struct clk_hw *hw,

				  struct clk_rate_request *req)

{

	unsigned long idiv;



	/* PLL cannot operate with input clock above 50 MHz. */

	if (rate > 50000000)

	if (req->rate > 50000000)

		return -EINVAL;



	/* CLKIN within range of PLL input, feed directly to PLL. */

	if (*parent_rate <= 50000000)

		return *parent_rate;

	if (req->best_parent_rate <= 50000000) {

		req->rate = req->best_parent_rate;



		return 0;

	}



	idiv = DIV_ROUND_UP(*parent_rate, rate);

	idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate);

	if (idiv > 127)

		return -EINVAL;



	return *parent_rate / idiv;

	req->rate = req->best_parent_rate / idiv;



	return 0;

}



static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -420,7 +425,7 @@ static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops vc5_pfd_ops = {

	.recalc_rate	= vc5_pfd_recalc_rate,

	.round_rate	= vc5_pfd_round_rate,

	.determine_rate = vc5_pfd_determine_rate,

	.set_rate	= vc5_pfd_set_rate,

};
@@ -444,30 +449,32 @@ static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, 
	return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);

}



static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,

			       unsigned long *parent_rate)

static int vc5_pll_determine_rate(struct clk_hw *hw,

				  struct clk_rate_request *req)

{

	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);

	struct vc5_driver_data *vc5 = hwdata->vc5;

	u32 div_int;

	u64 div_frc;



	rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);

	req->rate = clamp(req->rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);



	/* Determine integer part, which is 12 bit wide */

	div_int = rate / *parent_rate;

	div_int = req->rate / req->best_parent_rate;

	if (div_int > 0xfff)

		rate = *parent_rate * 0xfff;

		req->rate = req->best_parent_rate * 0xfff;



	/* Determine best fractional part, which is 24 bit wide */

	div_frc = rate % *parent_rate;

	div_frc = req->rate % req->best_parent_rate;

	div_frc *= BIT(24) - 1;

	do_div(div_frc, *parent_rate);

	do_div(div_frc, req->best_parent_rate);



	hwdata->div_int = div_int;

	hwdata->div_frc = (u32)div_frc;



	return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);

	req->rate = (req->best_parent_rate * div_int) + ((req->best_parent_rate * div_frc) >> 24);



	return 0;

}



static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -488,7 +495,7 @@ static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops vc5_pll_ops = {

	.recalc_rate	= vc5_pll_recalc_rate,

	.round_rate	= vc5_pll_round_rate,

	.determine_rate = vc5_pll_determine_rate,

	.set_rate	= vc5_pll_set_rate,

};
@@ -520,17 +527,17 @@ static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, 
	return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);

}



static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,

			       unsigned long *parent_rate)

static int vc5_fod_determine_rate(struct clk_hw *hw,

				  struct clk_rate_request *req)

{

	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);

	/* VCO frequency is divided by two before entering FOD */

	u32 f_in = *parent_rate / 2;

	u32 f_in = req->best_parent_rate / 2;

	u32 div_int;

	u64 div_frc;



	/* Determine integer part, which is 12 bit wide */

	div_int = f_in / rate;

	div_int = f_in / req->rate;

	/*

	 * WARNING: The clock chip does not output signal if the integer part

	 *          of the divider is 0xfff and fractional part is non-zero.
@@ -538,18 +545,20 @@ static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, 
	 */

	if (div_int > 0xffe) {

		div_int = 0xffe;

		rate = f_in / div_int;

		req->rate = f_in / div_int;

	}



	/* Determine best fractional part, which is 30 bit wide */

	div_frc = f_in % rate;

	div_frc = f_in % req->rate;

	div_frc <<= 24;

	do_div(div_frc, rate);

	do_div(div_frc, req->rate);



	hwdata->div_int = div_int;

	hwdata->div_frc = (u32)div_frc;



	return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);

	req->rate = div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);



	return 0;

}



static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -589,7 +598,7 @@ static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops vc5_fod_ops = {

	.recalc_rate	= vc5_fod_recalc_rate,

	.round_rate	= vc5_fod_round_rate,

	.determine_rate = vc5_fod_determine_rate,

	.set_rate	= vc5_fod_set_rate,

};