Commit 7c3fecdd authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Biju Das
Browse files

drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations 



Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.

These changes prepare the driver for upcoming RZ/V2H(P) SoC support.

Co-developed-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-7-prabhakar.mahadev-lad.rj@bp.renesas.com
parent e96bec00

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

+8 −5
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
struct rzg2l_mipi_dsi;



struct rzg2l_mipi_dsi_hw_info {

	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq);

	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);

	void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);

	u32 phy_reg_offset;

	u32 link_reg_offset;
@@ -210,8 +210,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) 
 */



static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,

				    unsigned long hsfreq)

				    u64 hsfreq_millihz)

{

	unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);

	const struct rzg2l_mipi_dsi_timings *dphy_timings;

	unsigned int i;

	u32 dphyctrl0;
@@ -284,6 +285,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, 
				  const struct drm_display_mode *mode)

{

	unsigned long hsfreq, vclk_rate;

	u64 hsfreq_millihz;

	unsigned int bpp;

	u32 txsetr;

	u32 clstptsetr;
@@ -316,9 +318,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, 
	 * hsclk(bit) = hsclk(byte) * 8 = hsfreq

	 */

	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

	hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);

	hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI), dsi->lanes);



	ret = dsi->info->dphy_init(dsi, hsfreq);

	ret = dsi->info->dphy_init(dsi, hsfreq_millihz);

	if (ret < 0)

		goto err_phy;
@@ -326,6 +328,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, 
	txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;

	rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);



	hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);

	/*

	 * Global timings characteristic depends on high speed Clock Frequency

	 * Currently MIPI DSI-IF just supports maximum FHD@60 with:
@@ -965,7 +968,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) 
	 * mode->clock and format are not available. So initialize DPHY with

	 * timing parameters for 80Mbps.

	 */

	ret = dsi->info->dphy_init(dsi, 80000000);

	ret = dsi->info->dphy_init(dsi, 80000000ULL * MILLI);

	if (ret < 0)

		goto err_phy;