Commit 7c4bf8cb authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
Browse files

phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650 



Add QMP UFS PHY support for the SM8650 platform.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-5-a543a4c4b491@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 330df15d

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#define QPHY_V6_PCS_UFS_SW_RESET			0x008

#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c

#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010

#define QPHY_V6_PCS_UFS_PCS_CTRL1			0x020

#define QPHY_V6_PCS_UFS_PLL_CNTL			0x02c

#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030

#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

+7 −0
Original line number Diff line number Diff line
@@ -10,10 +10,17 @@ 
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX			0x2c

#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX		0x30

#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX		0x34

#define QSERDES_UFS_V6_TX_LANE_MODE_1				0x7c



#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2		0x08

#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4		0x10

#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION			0x28

#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1				0x58

#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0			0xc4

#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2			0xd4

#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4			0xdc

#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL			0x178

#define QSERDES_UFS_V6_RX_INTERFACE_MODE			0x1e0

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0			0x208

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1			0x20c

#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3			0x214

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+86 −0
Original line number Diff line number Diff line
@@ -803,6 +803,67 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),

};



static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



struct qmp_ufs_offsets {

	u16 serdes;

	u16 pcs;
@@ -1303,6 +1364,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 
	.regs			= ufsphy_v6_regs_layout,

};



static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_ufs_offsets_v6,



	.tbls = {

		.serdes		= sm8650_ufsphy_serdes,

		.serdes_num	= ARRAY_SIZE(sm8650_ufsphy_serdes),

		.tx		= sm8650_ufsphy_tx,

		.tx_num		= ARRAY_SIZE(sm8650_ufsphy_tx),

		.rx		= sm8650_ufsphy_rx,

		.rx_num		= ARRAY_SIZE(sm8650_ufsphy_rx),

		.pcs		= sm8650_ufsphy_pcs,

		.pcs_num	= ARRAY_SIZE(sm8650_ufsphy_pcs),

	},

	.clk_list		= sdm845_ufs_phy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= ufsphy_v6_regs_layout,

};



static void qmp_ufs_configure_lane(void __iomem *base,

					const struct qmp_phy_init_tbl tbl[],

					int num,
@@ -1826,6 +1909,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8550-qmp-ufs-phy",

		.data = &sm8550_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm8650-qmp-ufs-phy",

		.data = &sm8650_ufsphy_cfg,

	},

	{ },

};