Commit 7c775c60 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "A bunch of new device support and updates to few drivers, biggest of
  them amd ones.

  New support:
   - TI J722S CSI BCDMA controller support
   - Intel idxd Panther Lake family platforms
   - Allwinner F1C100s suniv DMA
   - Qualcomm QCS615, QCS8300, SM8750, SA8775P GPI dma controller support
   - AMD ae4dma controller support and reorganisation of amd driver

  Updates:
   - Channel page support for Nvidia Tegra210 adma driver
   - Freescale support for S32G based platforms
   - Yamilfy atmel dma bindings"

* tag 'dmaengine-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (45 commits)
  dmaengine: idxd: Enable Function Level Reset (FLR) for halt
  dmaengine: idxd: Refactor halt handler
  dmaengine: idxd: Add idxd_device_config_save() and idxd_device_config_restore() helpers
  dmaengine: idxd: Binding and unbinding IDXD device and driver
  dmaengine: idxd: Add idxd_pci_probe_alloc() helper
  dt-bindings: dma: atmel: Convert to json schema
  dt-bindings: dma: st-stm32-dmamux: Add description for dma-cell values
  dmaengine: qcom: gpi: Add GPI immediate DMA support for SPI protocol
  dt-bindings: dma: adi,axi-dmac: deprecate adi,channels node
  dt-bindings: dma: adi,axi-dmac: convert to yaml schema
  dmaengine: mv_xor: switch to for_each_child_of_node_scoped()
  dmaengine: bcm2835-dma: Prevent suspend if DMA channel is busy
  dmaengine: tegra210-adma: Support channel page
  dt-bindings: dma: Support channel page to nvidia,tegra210-adma
  dmaengine: ti: k3-udma: Add support for J722S CSI BCDMA
  dt-bindings: dma: ti: k3-bcdma: Add J722S CSI BCDMA
  dmaengine: ti: edma: fix OF node reference leaks in edma_driver
  dmaengine: ti: edma: make the loop condition simpler in edma_probe()
  dmaengine: fsl-edma: read/write multiple registers in cyclic transactions
  dmaengine: fsl-edma: add support for S32G based platforms
  ...
parents ebbb8be4 98d187a9

Documentation/devicetree/bindings/dma/adi,axi-dmac.txt

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Analog Devices AXI-DMAC DMA controller



Required properties:

 - compatible: Must be "adi,axi-dmac-1.00.a".

 - reg: Specification for the controllers memory mapped register map.

 - interrupts: Specification for the controllers interrupt.

 - clocks: Phandle and specifier to the controllers AXI interface clock

 - #dma-cells: Must be 1.



Required sub-nodes:

 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For

   the channel sub-nodes the following bindings apply. They must match the

   configuration options of the peripheral as it was instantiated.



Required properties for adi,channels sub-node:

 - #size-cells: Must be 0

 - #address-cells: Must be 1



Required channel sub-node properties:

 - reg: Which channel this node refers to.

 - adi,source-bus-width,

   adi,destination-bus-width: Width of the source or destination bus in bits.

 - adi,source-bus-type,

   adi,destination-bus-type: Type of the source or destination bus. Must be one

   of the following:

	0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface

	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface

	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface



Deprecated optional channel properties:

 - adi,length-width: Width of the DMA transfer length register.

 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA

   transfers.

 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.



DMA clients connected to the AXI-DMAC DMA controller must use the format

described in the dma.txt file using a one-cell specifier. The value of the

specifier refers to the DMA channel index.



Example:



dma: dma@7c420000 {

	compatible = "adi,axi-dmac-1.00.a";

	reg = <0x7c420000 0x10000>;

	interrupts = <0 57 0>;

	clocks = <&clkc 16>;

	#dma-cells = <1>;



	adi,channels {

		#size-cells = <0>;

		#address-cells = <1>;



		dma-channel@0 {

			reg = <0>;

			adi,source-bus-width = <32>;

			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;

			adi,destination-bus-width = <64>;

			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;

		};

	};

};

Documentation/devicetree/bindings/dma/adi,axi-dmac.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Analog Devices AXI-DMAC DMA controller



description: |

  FPGA-based DMA controller designed for use with high-speed converter hardware.



  http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html



maintainers:

  - Nuno Sa <nuno.sa@analog.com>



additionalProperties: false



properties:

  compatible:

    const: adi,axi-dmac-1.00.a



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  "#dma-cells":

    const: 1



  adi,channels:

    deprecated: true

    type: object

    description:

      This sub-node must contain a sub-node for each DMA channel. This node is

      only required for IP versions older than 4.3.a and should otherwise be

      omitted.

    additionalProperties: false



    properties:

      "#size-cells":

        const: 0

      "#address-cells":

        const: 1



    patternProperties:

      "^dma-channel@[0-9a-f]+$":

        type: object

        description:

          DMA channel properties based on HDL compile-time configuration.

        additionalProperties: false



        properties:

          reg:

            maxItems: 1



          adi,source-bus-width:

            $ref: /schemas/types.yaml#/definitions/uint32

            description: Width of the source bus in bits.

            enum: [8, 16, 32, 64, 128]



          adi,destination-bus-width:

            $ref: /schemas/types.yaml#/definitions/uint32

            description: Width of the destination bus in bits.

            enum: [8, 16, 32, 64, 128]



          adi,source-bus-type:

            $ref: /schemas/types.yaml#/definitions/uint32

            description: |

              Type of the source bus.



              0: Memory mapped AXI interface

              1: Streaming AXI interface

              2: FIFO interface

            enum: [0, 1, 2]



          adi,destination-bus-type:

            $ref: /schemas/types.yaml#/definitions/uint32

            description: Type of the destination bus (see adi,source-bus-type).

            enum: [0, 1, 2]



          adi,length-width:

            deprecated: true

            $ref: /schemas/types.yaml#/definitions/uint32

            description: Width of the DMA transfer length register.



          adi,cyclic:

            deprecated: true

            type: boolean

            description:

              Must be set if the channel supports hardware cyclic DMA transfers.



          adi,2d:

            deprecated: true

            type: boolean

            description:

              Must be set if the channel supports hardware 2D DMA transfers.



        required:

          - reg

          - adi,source-bus-width

          - adi,destination-bus-width

          - adi,source-bus-type

          - adi,destination-bus-type



    required:

      - "#size-cells"

      - "#address-cells"



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - "#dma-cells"



examples:

  - |

    dma-controller@7c420000 {

        compatible = "adi,axi-dmac-1.00.a";

        reg = <0x7c420000 0x10000>;

        interrupts = <0 57 0>;

        clocks = <&clkc 16>;

        #dma-cells = <1>;

    };

Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml

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@@ -22,7 +22,9 @@ properties: 
      number.



  compatible:

    const: allwinner,sun4i-a10-dma

    enum:

      - allwinner,sun4i-a10-dma

      - allwinner,suniv-f1c100s-dma



  reg:

    maxItems: 1

Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip AT91 Extensible Direct Memory Access Controller



maintainers:

  - Nicolas Ferre <nicolas.ferre@microchip.com>

  - Charan Pedumuru <charan.pedumuru@microchip.com>



description:

  The DMA Controller (XDMAC) is a AHB-protocol central direct memory access

  controller. It performs peripheral data transfer and memory move operations

  over one or two bus ports through the unidirectional communication

  channel. Each channel is fully programmable and provides both peripheral

  or memory-to-memory transfers. The channel features are configurable at

  implementation.



allOf:

  - $ref: dma-controller.yaml#



properties:

  compatible:

    oneOf:

      - enum:

          - atmel,sama5d4-dma

          - microchip,sama7g5-dma

      - items:

          - enum:

              - microchip,sam9x60-dma

              - microchip,sam9x7-dma

          - const: atmel,sama5d4-dma



  "#dma-cells":

    description: |

      Represents the number of integer cells in the `dmas` property of client

      devices. The single cell specifies the channel configuration register:

        - bit 13: SIF (Source Interface Identifier) for memory interface.

        - bit 14: DIF (Destination Interface Identifier) for peripheral interface.

        - bit 30-24: PERID (Peripheral Identifier).

    const: 1



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: dma_clk



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#dma-cells"



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/at91.h>

    #include <dt-bindings/dma/at91.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    dma-controller@f0008000 {

        compatible = "atmel,sama5d4-dma";

        reg = <0xf0008000 0x1000>;

        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;

        #dma-cells = <1>;

        clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;

        clock-names = "dma_clk";

    };

Documentation/devicetree/bindings/dma/atmel-xdma.txt

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* Atmel Extensible Direct Memory Access Controller (XDMAC)



* XDMA Controller

Required properties:

- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or

  "microchip,sama7g5-dma" or

  "microchip,sam9x7-dma", "atmel,sama5d4-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <1>, used to represent the number of integer cells in

the dmas property of client devices.

  - The 1st cell specifies the channel configuration register:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

    - bit 30-24: PERID, peripheral identifier.



Example:



dma1: dma-controller@f0004000 {

	compatible = "atmel,sama5d4-dma";

	reg = <0xf0004000 0x200>;

	interrupts = <50 4 0>;

	#dma-cells = <1>;

};





* DMA clients

DMA clients connected to the Atmel XDMA controller must use the format

described in the dma.txt file, using a one-cell specifier for each channel.

The two cells in order are:

1. A phandle pointing to the DMA controller.

2. Channel configuration register. Configurable fields are:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

  - bit 30-24: PERID, peripheral identifier.



Example:



i2c2: i2c@f8024000 {

	compatible = "atmel,at91sam9x5-i2c";

	reg = <0xf8024000 0x4000>;

	interrupts = <34 4 6>;

	dmas = <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		 | AT91_XDMAC_DT_PERID(6))>,

	       <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		| AT91_XDMAC_DT_PERID(7))>;

	dma-names = "tx", "rx";

};