Commit 7c7f9dd1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.16-1-2025-06-20' of... 

Merge tag 'perf-tools-fixes-for-v6.16-1-2025-06-20' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Arnaldo Carvalho de Melo:

 - Fix some file descriptor leaks that stand out with recent changes to
   'perf list'

 - Fix prctl include to fix building 'perf bench futex' hash with musl
   libc

 - Restrict 'perf test' uniquifying entry to machines with 'uncore_imc'
   PMUs

 - Document new output fields (op, cache, mem, dtlb, snoop) used with
   'perf mem'

 - Synchronize kernel header copies

* tag 'perf-tools-fixes-for-v6.16-1-2025-06-20' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  tools headers x86 cpufeatures: Sync with the kernel sources
  perf bench futex: Fix prctl include in musl libc
  perf test: Directory file descriptor leak
  perf evsel: Missed close() when probing hybrid core PMUs
  tools headers: Synchronize linux/bits.h with the kernel sources
  tools arch amd ibs: Sync ibs.h with the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  tools headers: Syncronize linux/build_bug.h with the kernel sources
  tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench'
  tools headers UAPI: Sync linux/kvm.h with the kernel sources
  tools headers UAPI: Sync the drm/drm.h with the kernel sources
  perf beauty: Update copy of linux/socket.h with the kernel sources
  tools headers UAPI: Sync kvm header with the kernel sources
  tools headers x86 svm: Sync svm headers with the kernel sources
  tools headers UAPI: Sync KVM's vmx.h header with the kernel sources
  tools kvm headers arm64: Update KVM header from the kernel sources
  tools headers UAPI: Sync linux/prctl.h with the kernel sources to pick FUTEX knob
  perf mem: Document new output fields (op, cache, mem, dtlb, snoop)
  tools headers: Update the fs headers with the kernel sources
  perf test: Restrict uniquifying test to machines with 'uncore_imc'
parents 3f75bfff d222b6e6

include/uapi/linux/bits.h

+2 −2
Original line number Diff line number Diff line
@@ -4,9 +4,9 @@ 
#ifndef _UAPI_LINUX_BITS_H

#define _UAPI_LINUX_BITS_H



#define __GENMASK(h, l) (((~_UL(0)) << (l)) & (~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))

#define __GENMASK(h, l) (((~_UL(0)) << (l)) & (~_UL(0) >> (BITS_PER_LONG - 1 - (h))))



#define __GENMASK_ULL(h, l) (((~_ULL(0)) << (l)) & (~_ULL(0) >> (__BITS_PER_LONG_LONG - 1 - (h))))

#define __GENMASK_ULL(h, l) (((~_ULL(0)) << (l)) & (~_ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h))))



#define __GENMASK_U128(h, l) \

	((_BIT128((h)) << 1) - (_BIT128(l)))

tools/arch/arm64/include/uapi/asm/kvm.h

+5 −4
Original line number Diff line number Diff line
@@ -435,6 +435,7 @@ enum { 
#define   KVM_ARM_VCPU_PMU_V3_INIT		1

#define   KVM_ARM_VCPU_PMU_V3_FILTER		2

#define   KVM_ARM_VCPU_PMU_V3_SET_PMU		3

#define   KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS	4

#define KVM_ARM_VCPU_TIMER_CTRL		1

#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0

#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1

tools/arch/x86/include/asm/amd/ibs.h

+5 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_X86_AMD_IBS_H

#define _ASM_X86_AMD_IBS_H



/*

 * From PPR Vol 1 for AMD Family 19h Model 01h B1

 * 55898 Rev 0.35 - Feb 5, 2021
@@ -151,3 +154,5 @@ struct perf_ibs_data { 
	};

	u64		regs[MSR_AMD64_IBS_REG_COUNT_MAX];

};



#endif /* _ASM_X86_AMD_IBS_H */

tools/arch/x86/include/asm/cpufeatures.h

+10 −4
Original line number Diff line number Diff line
@@ -379,6 +379,7 @@ 
#define X86_FEATURE_V_SPEC_CTRL		(15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */

#define X86_FEATURE_VNMI		(15*32+25) /* "vnmi" Virtual NMI */

#define X86_FEATURE_SVME_ADDR_CHK	(15*32+28) /* SVME addr check */

#define X86_FEATURE_BUS_LOCK_THRESHOLD	(15*32+29) /* Bus lock threshold */

#define X86_FEATURE_IDLE_HLT		(15*32+30) /* IDLE HLT intercept */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
@@ -447,6 +448,7 @@ 
#define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */

#define X86_FEATURE_RMPREAD		(19*32+21) /* RMPREAD instruction */

#define X86_FEATURE_SEGMENTED_RMP	(19*32+23) /* Segmented RMP support */

#define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* Allowed SEV Features */

#define X86_FEATURE_SVSM		(19*32+28) /* "svsm" SVSM present */

#define X86_FEATURE_HV_INUSE_WR_ALLOWED	(19*32+30) /* Allow Write to in-use hypervisor-owned pages */
@@ -458,6 +460,7 @@ 
#define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */

#define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */



#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */

#define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */

#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */

#define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */
@@ -482,7 +485,8 @@ 
#define X86_FEATURE_AMD_HTR_CORES	(21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */

#define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */

#define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+ 9) /* Use thunk for indirect branches in lower half of cacheline */

#define X86_FEATURE_APX			(21*32+ 9) /* Advanced Performance Extensions */

#define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+10) /* Use thunk for indirect branches in lower half of cacheline */



/*

 * BUG word(s)
@@ -535,6 +539,8 @@ 
#define X86_BUG_BHI			X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */

#define X86_BUG_IBPB_NO_RET		X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target predictions */

#define X86_BUG_SPECTRE_V2_USER		X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */

#define X86_BUG_ITS			X86_BUG( 1*32+ 6) /* "its" CPU is affected by Indirect Target Selection */

#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 7) /* "its_native_only" CPU is affected by ITS, VMX is not affected */

#define X86_BUG_OLD_MICROCODE		X86_BUG( 1*32+ 6) /* "old_microcode" CPU has old microcode, it is surely vulnerable to something */

#define X86_BUG_ITS			X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indirect Target Selection */

#define X86_BUG_ITS_NATIVE_ONLY		X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX is not affected */



#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/msr-index.h

+10 −6
Original line number Diff line number Diff line
@@ -553,13 +553,13 @@ 
#define HWP_MIN_PERF(x)			(x & 0xff)

#define HWP_MAX_PERF(x)			((x & 0xff) << 8)

#define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)

#define HWP_ENERGY_PERF_PREFERENCE(x)	(((unsigned long long) x & 0xff) << 24)

#define HWP_ENERGY_PERF_PREFERENCE(x)	(((u64)x & 0xff) << 24)

#define HWP_EPP_PERFORMANCE		0x00

#define HWP_EPP_BALANCE_PERFORMANCE	0x80

#define HWP_EPP_BALANCE_POWERSAVE	0xC0

#define HWP_EPP_POWERSAVE		0xFF

#define HWP_ACTIVITY_WINDOW(x)		((unsigned long long)(x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((unsigned long long)(x & 0x1) << 42)

#define HWP_ACTIVITY_WINDOW(x)		((u64)(x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((u64)(x & 0x1) << 42)



/* IA32_HWP_STATUS */

#define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
@@ -602,7 +602,11 @@ 
/* V6 PMON MSR range */

#define MSR_IA32_PMC_V6_GP0_CTR		0x1900

#define MSR_IA32_PMC_V6_GP0_CFG_A	0x1901

#define MSR_IA32_PMC_V6_GP0_CFG_B	0x1902

#define MSR_IA32_PMC_V6_GP0_CFG_C	0x1903

#define MSR_IA32_PMC_V6_FX0_CTR		0x1980

#define MSR_IA32_PMC_V6_FX0_CFG_B	0x1982

#define MSR_IA32_PMC_V6_FX0_CFG_C	0x1983

#define MSR_IA32_PMC_V6_STEP		4



/* KeyID partitioning between MKTME and TDX */