Loading arch/mips/include/asm/irq.h +2 −2 Original line number Diff line number Diff line Loading @@ -55,8 +55,8 @@ static inline void smtc_im_ack_irq(unsigned int irq) #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF #include <linux/cpumask.h> extern int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity); extern int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force); extern void smtc_forward_irq(unsigned int irq); /* Loading arch/mips/kernel/i8259.c +17 −20 Original line number Diff line number Diff line Loading @@ -31,19 +31,19 @@ static int i8259A_auto_eoi = -1; DEFINE_RAW_SPINLOCK(i8259A_lock); static void disable_8259A_irq(unsigned int irq); static void enable_8259A_irq(unsigned int irq); static void mask_and_ack_8259A(unsigned int irq); static void disable_8259A_irq(struct irq_data *d); static void enable_8259A_irq(struct irq_data *d); static void mask_and_ack_8259A(struct irq_data *d); static void init_8259A(int auto_eoi); static struct irq_chip i8259A_chip = { .name = "XT-PIC", .mask = disable_8259A_irq, .disable = disable_8259A_irq, .unmask = enable_8259A_irq, .mask_ack = mask_and_ack_8259A, .irq_mask = disable_8259A_irq, .irq_disable = disable_8259A_irq, .irq_unmask = enable_8259A_irq, .irq_mask_ack = mask_and_ack_8259A, #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF .set_affinity = plat_set_irq_affinity, .irq_set_affinity = plat_set_irq_affinity, #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; Loading @@ -59,12 +59,11 @@ static unsigned int cached_irq_mask = 0xffff; #define cached_master_mask (cached_irq_mask) #define cached_slave_mask (cached_irq_mask >> 8) static void disable_8259A_irq(unsigned int irq) static void disable_8259A_irq(struct irq_data *d) { unsigned int mask; unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; mask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; Loading @@ -75,12 +74,11 @@ static void disable_8259A_irq(unsigned int irq) raw_spin_unlock_irqrestore(&i8259A_lock, flags); } static void enable_8259A_irq(unsigned int irq) static void enable_8259A_irq(struct irq_data *d) { unsigned int mask; unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; mask = ~(1 << irq); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; Loading Loading @@ -145,12 +143,11 @@ static inline int i8259A_irq_real(unsigned int irq) * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ static void mask_and_ack_8259A(unsigned int irq) static void mask_and_ack_8259A(struct irq_data *d) { unsigned int irqmask; unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; irqmask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); /* Loading Loading @@ -290,9 +287,9 @@ static void init_8259A(int auto_eoi) * In AEOI mode we just have to mask the interrupt * when acking. */ i8259A_chip.mask_ack = disable_8259A_irq; i8259A_chip.irq_mask_ack = disable_8259A_irq; else i8259A_chip.mask_ack = mask_and_ack_8259A; i8259A_chip.irq_mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ Loading arch/mips/mti-malta/malta-smtc.c +5 −4 Original line number Diff line number Diff line Loading @@ -113,7 +113,8 @@ struct plat_smp_ops msmtc_smp_ops = { */ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { cpumask_t tmask; int cpu = 0; Loading Loading @@ -143,7 +144,7 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) cpu_clear(cpu, tmask); } cpumask_copy(irq_desc[irq].affinity, &tmask); cpumask_copy(d->affinity, &tmask); if (cpus_empty(tmask)) /* Loading @@ -154,8 +155,8 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); /* Do any generic SMTC IRQ affinity setup */ smtc_set_irq_affinity(irq, tmask); smtc_set_irq_affinity(d->irq, tmask); return 0; return IRQ_SET_MASK_OK_NOCOPY; } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ Loading
arch/mips/include/asm/irq.h +2 −2 Original line number Diff line number Diff line Loading @@ -55,8 +55,8 @@ static inline void smtc_im_ack_irq(unsigned int irq) #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF #include <linux/cpumask.h> extern int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity); extern int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force); extern void smtc_forward_irq(unsigned int irq); /* Loading
arch/mips/kernel/i8259.c +17 −20 Original line number Diff line number Diff line Loading @@ -31,19 +31,19 @@ static int i8259A_auto_eoi = -1; DEFINE_RAW_SPINLOCK(i8259A_lock); static void disable_8259A_irq(unsigned int irq); static void enable_8259A_irq(unsigned int irq); static void mask_and_ack_8259A(unsigned int irq); static void disable_8259A_irq(struct irq_data *d); static void enable_8259A_irq(struct irq_data *d); static void mask_and_ack_8259A(struct irq_data *d); static void init_8259A(int auto_eoi); static struct irq_chip i8259A_chip = { .name = "XT-PIC", .mask = disable_8259A_irq, .disable = disable_8259A_irq, .unmask = enable_8259A_irq, .mask_ack = mask_and_ack_8259A, .irq_mask = disable_8259A_irq, .irq_disable = disable_8259A_irq, .irq_unmask = enable_8259A_irq, .irq_mask_ack = mask_and_ack_8259A, #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF .set_affinity = plat_set_irq_affinity, .irq_set_affinity = plat_set_irq_affinity, #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; Loading @@ -59,12 +59,11 @@ static unsigned int cached_irq_mask = 0xffff; #define cached_master_mask (cached_irq_mask) #define cached_slave_mask (cached_irq_mask >> 8) static void disable_8259A_irq(unsigned int irq) static void disable_8259A_irq(struct irq_data *d) { unsigned int mask; unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; mask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; Loading @@ -75,12 +74,11 @@ static void disable_8259A_irq(unsigned int irq) raw_spin_unlock_irqrestore(&i8259A_lock, flags); } static void enable_8259A_irq(unsigned int irq) static void enable_8259A_irq(struct irq_data *d) { unsigned int mask; unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; mask = ~(1 << irq); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; Loading Loading @@ -145,12 +143,11 @@ static inline int i8259A_irq_real(unsigned int irq) * first, _then_ send the EOI, and the order of EOI * to the two 8259s is important! */ static void mask_and_ack_8259A(unsigned int irq) static void mask_and_ack_8259A(struct irq_data *d) { unsigned int irqmask; unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; unsigned long flags; irq -= I8259A_IRQ_BASE; irqmask = 1 << irq; raw_spin_lock_irqsave(&i8259A_lock, flags); /* Loading Loading @@ -290,9 +287,9 @@ static void init_8259A(int auto_eoi) * In AEOI mode we just have to mask the interrupt * when acking. */ i8259A_chip.mask_ack = disable_8259A_irq; i8259A_chip.irq_mask_ack = disable_8259A_irq; else i8259A_chip.mask_ack = mask_and_ack_8259A; i8259A_chip.irq_mask_ack = mask_and_ack_8259A; udelay(100); /* wait for 8259A to initialize */ Loading
arch/mips/mti-malta/malta-smtc.c +5 −4 Original line number Diff line number Diff line Loading @@ -113,7 +113,8 @@ struct plat_smp_ops msmtc_smp_ops = { */ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { cpumask_t tmask; int cpu = 0; Loading Loading @@ -143,7 +144,7 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) cpu_clear(cpu, tmask); } cpumask_copy(irq_desc[irq].affinity, &tmask); cpumask_copy(d->affinity, &tmask); if (cpus_empty(tmask)) /* Loading @@ -154,8 +155,8 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); /* Do any generic SMTC IRQ affinity setup */ smtc_set_irq_affinity(irq, tmask); smtc_set_irq_affinity(d->irq, tmask); return 0; return IRQ_SET_MASK_OK_NOCOPY; } #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */