Unverified Commit 7c9bb190 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-fixes-6.7' of... 

Merge tag 'imx-fixes-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.7:

- A MAINTAINERS update to reinstate freescale ARM64 DT directory in i.MX
  entry.
- A series from Alexander Stein to fix #pwm-cells for imx8-ss.
- A series from Haibo Chen to fix GPIO node name for i.MX93 and
  i.MX8ULP.
- Add parkmode-disable-ss-quirk for DWC3 on i.MX8MP and i.MX8MQ to fix
  an issue that the controller may hang when processing transactions
  under heavy USB traffic from multiple endpoints.
- Fix mediamix block power on/off for i.MX93 by correcting the power
  domain clock to be 'nic_media'.
- A couple of Ethernet PHY clock regression fixes for imx6ul-pico and
  imx6q-skov board.
- Fix edma3 power domain for i.MX8QM to fix a panic during startup
  process.

* tag 'imx-fixes-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx28-xea: Pass the 'model' property
  ARM: dts: imx7: Declare timers compatible with fsl,imx6dl-gpt
  MAINTAINERS: reinstate freescale ARM64 DT directory in i.MX entry
  arm64: dts: imx8-apalis: set wifi regulator to always-on
  ARM: imx: Check return value of devm_kasprintf in imx_mmdc_perf_init
  arm64: dts: imx8ulp: update gpio node name to align with register address
  arm64: dts: imx93: update gpio node name to align with register address
  arm64: dts: imx93: correct mediamix power
  arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup
  arm64: dts: freescale: imx8-ss-dma: Fix #pwm-cells
  arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells
  dt-bindings: pwm: imx-pwm: Unify #pwm-cells for all compatibles
  ARM: dts: imx6ul-pico: Describe the Ethernet PHY clock
  arm64: dts: imx8mp: imx8mq: Add parkmode-disable-ss-quirk on DWC3
  ARM: dts: imx6q: skov: fix ethernet clock regression
  arm64: dt: imx93: tqma9352-mba93xxla: Fix LPUART2 pad config

Link: https://lore.kernel.org/r/20231207005202.GF270430@dragon


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents b0b2981c 63ef8fc9

Documentation/devicetree/bindings/pwm/imx-pwm.yaml

+4 −6
Original line number Diff line number Diff line
@@ -14,12 +14,10 @@ allOf: 


properties:

  "#pwm-cells":

    description: |

      Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml

      in this directory for a description of the cells format.

    enum:

      - 2

      - 3

    description:

      The only third cell flag supported by this binding is

      PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.

    const: 3



  compatible:

    oneOf:

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -2155,6 +2155,7 @@ S: Maintained 
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git

F:	arch/arm/boot/dts/nxp/imx/

F:	arch/arm/boot/dts/nxp/mxs/

F:	arch/arm64/boot/dts/freescale/

X:	arch/arm64/boot/dts/freescale/fsl-*

X:	arch/arm64/boot/dts/freescale/qoriq-*

X:	drivers/media/i2c/

arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts

+2 −2
Original line number Diff line number Diff line
@@ -37,9 +37,9 @@ panel_in: endpoint { 


&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;

				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;

};



&hdmi {

arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -121,6 +121,8 @@ ethphy1: ethernet-phy@1 { 
			max-speed = <100>;

			interrupt-parent = <&gpio5>;

			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&clks IMX6UL_CLK_ENET_REF>;

			clock-names = "rmii-ref";

		};

	};

};

arch/arm/boot/dts/nxp/imx/imx7s.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -454,7 +454,7 @@ iomuxc_lpsr: pinctrl@302c0000 { 
			};



			gpt1: timer@302d0000 {

				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";

				reg = <0x302d0000 0x10000>;

				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
@@ -463,7 +463,7 @@ gpt1: timer@302d0000 { 
			};



			gpt2: timer@302e0000 {

				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";

				reg = <0x302e0000 0x10000>;

				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
@@ -473,7 +473,7 @@ gpt2: timer@302e0000 { 
			};



			gpt3: timer@302f0000 {

				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";

				reg = <0x302f0000 0x10000>;

				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
@@ -483,7 +483,7 @@ gpt3: timer@302f0000 { 
			};



			gpt4: timer@30300000 {

				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";

				compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";

				reg = <0x30300000 0x10000>;

				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_GPT4_ROOT_CLK>,