Commit 7ce3c271 authored by Michal Simek's avatar Michal Simek Committed by Rob Herring (Arm)
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dt-bindings: interrupt-controller: Add missing Xilinx INTC binding 



Add missing description for AMD/Xilinx interrupt controller. The binding is
used by Microblaze before dt-binding even existed but never been
documented properly.

IP acts as primary interrupt controller on Microblaze systems or can be
used as secondary interrupt controller on ARM based systems like Zynq,
ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
Microblaze-V (Risc-V) systems.

Over the years IP exists in multiple variants based on attached bus as OPB,
PLB or AXI that's why generic filename is used.

Property xlnx,kind-of-intr is in hex because every bit position corresponds
to interrupt line. Controller support mixing edge or level interrupts
together and this is the property which distinguish them.

Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/2b9d4a3a693f501d420da88b8418732ba9def877.1753354675.git.michal.simek@amd.com


Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent 2558df8c

Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx Interrupt Controller



maintainers:

  - Michal Simek <michal.simek@amd.com>



description:

  The controller is a soft IP core that is configured at build time for the

  number of interrupts and the type of each interrupt. These details cannot

  be changed at run time.



properties:

  compatible:

    const: xlnx,xps-intc-1.00.a



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  "#interrupt-cells":

    const: 2

    description:

      Specifies the number of cells needed to encode an interrupt source.

      The value shall be a minimum of 1. The Xilinx device trees typically

      use 2 but the 2nd value is not used.



  interrupt-controller: true



  interrupts:

    maxItems: 1

    description:

      Specifies the interrupt of the parent controller from which it is chained.



  xlnx,kind-of-intr:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      A 32 bit value specifying the interrupt type for each possible interrupt

      (1 = edge, 0 = level). The interrupt type typically comes in thru

      the device tree node of the interrupt generating device, but in this case

      the interrupt type is determined by the interrupt controller based on how

      it was implemented.



  xlnx,num-intr-inputs:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1

    maximum: 32

    description:

      Specifies the number of interrupts supported by the specific

      implementation of the controller.



required:

  - reg

  - "#interrupt-cells"

  - interrupt-controller

  - xlnx,kind-of-intr

  - xlnx,num-intr-inputs



additionalProperties: false



examples:

  - |

    interrupt-controller@41800000 {

      compatible = "xlnx,xps-intc-1.00.a";

      reg = <0x41800000 0x10000>;

      #interrupt-cells = <2>;

      interrupt-controller;

      xlnx,kind-of-intr = <0x1>;

      xlnx,num-intr-inputs = <1>;

    };