Commit 7d1158c9 authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes 



Add PCIe controllers and PHY nodes.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230118230526.1499328-2-abel.vesa@linaro.org
parent 6c409f63

arch/arm64/boot/dts/qcom/sm8550.dtsi

+210 −3
Original line number Diff line number Diff line
@@ -740,9 +740,9 @@ gcc: clock-controller@100000 { 
			#reset-cells = <1>;

			#power-domain-cells = <1>;

			clocks = <&bi_tcxo_div2>, <&sleep_clk>,

				 <0>,

				 <0>,

				 <0>,

				 <&pcie0_phy>,

				 <&pcie1_phy>,

				 <&pcie_1_phy_aux_clk>,

				 <&ufs_mem_phy 0>,

				 <&ufs_mem_phy 1>,

				 <&ufs_mem_phy 2>,
@@ -1641,6 +1641,213 @@ mmss_noc: interconnect@1780000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		pcie0: pci@1c00000 {

			device_type = "pci";

			compatible = "qcom,pcie-sm8550";

			reg = <0 0x01c00000 0 0x3000>,

			      <0 0x60000000 0 0xf1d>,

			      <0 0x60000f20 0 0xa8>,

			      <0 0x60001000 0 0x1000>,

			      <0 0x60100000 0 0x100000>;

			reg-names = "parf", "dbi", "elbi", "atu", "config";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,

				 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;

			bus-range = <0x00 0xff>;



			dma-coherent;



			linux,pci-domain = <0>;

			num-lanes = <2>;



			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";



			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,

				 <&gcc GCC_PCIE_0_AUX_CLK>,

				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,

				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,

				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;

			clock-names = "pipe",

				      "aux",

				      "cfg",

				      "bus_master",

				      "bus_slave",

				      "slave_q2a",

				      "ddrss_sf_tbu",

				      "aggre0";



			interconnect-names = "pcie-mem";

			interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;



			iommus = <&apps_smmu 0x1400 0x7f>;

			iommu-map = <0x0   &apps_smmu 0x1400 0x1>,

				    <0x100 &apps_smmu 0x1401 0x1>;



			resets = <&gcc GCC_PCIE_0_BCR>;

			reset-names = "pci";



			power-domains = <&gcc PCIE_0_GDSC>;



			phys = <&pcie0_phy>;

			phy-names = "pciephy";



			perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

			wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;



			pinctrl-names = "default";

			pinctrl-0 = <&pcie0_default_state>;



			status = "disabled";

		};



		pcie0_phy: phy@1c06000 {

			compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";

			reg = <0 0x01c06000 0 0x2000>;



			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,

				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,

				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_0_PIPE_CLK>;

			clock-names = "aux", "cfg_ahb", "ref", "rchng",

				      "pipe";



			resets = <&gcc GCC_PCIE_0_PHY_BCR>;

			reset-names = "phy";



			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;

			assigned-clock-rates = <100000000>;



			power-domains = <&gcc PCIE_0_PHY_GDSC>;



			#clock-cells = <0>;

			clock-output-names = "pcie0_pipe_clk";



			#phy-cells = <0>;



			status = "disabled";

		};



		pcie1: pci@1c08000 {

			device_type = "pci";

			compatible = "qcom,pcie-sm8550";

			reg = <0x0 0x01c08000 0x0 0x3000>,

			      <0x0 0x40000000 0x0 0xf1d>,

			      <0x0 0x40000f20 0x0 0xa8>,

			      <0x0 0x40001000 0x0 0x1000>,

			      <0x0 0x40100000 0x0 0x100000>;

			reg-names = "parf", "dbi", "elbi", "atu", "config";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,

				 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;

			bus-range = <0x00 0xff>;



			dma-coherent;



			linux,pci-domain = <1>;

			num-lanes = <2>;



			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";



			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,

				 <&gcc GCC_PCIE_1_AUX_CLK>,

				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,

				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,

				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,

				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,

				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;

			clock-names = "pipe",

				      "aux",

				      "cfg",

				      "bus_master",

				      "bus_slave",

				      "slave_q2a",

				      "ddrss_sf_tbu",

				      "aggre1",

				      "cnoc_pcie_sf_axi";



			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;

			assigned-clock-rates = <19200000>;



			interconnect-names = "pcie-mem";

			interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;



			iommus = <&apps_smmu 0x1480 0x7f>;

			iommu-map = <0x0   &apps_smmu 0x1480 0x1>,

				    <0x100 &apps_smmu 0x1481 0x1>;



			resets = <&gcc GCC_PCIE_1_BCR>,

				<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;

			reset-names = "pci",

				"pcie_1_link_down_reset";



			power-domains = <&gcc PCIE_1_GDSC>;



			phys = <&pcie1_phy>;

			phy-names = "pciephy";



			perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;

			enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;



			pinctrl-names = "default";

			pinctrl-0 = <&pcie1_default_state>;



			status = "disabled";

		};



		pcie1_phy: phy@1c0e000 {

			compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";

			reg = <0x0 0x01c0e000 0x0 0x2000>;



			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,

				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,

				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,

				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_1_PIPE_CLK>,

				 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;

			clock-names = "aux", "cfg_ahb", "ref", "rchng",

				      "pipe", "aux_phy";



			resets = <&gcc GCC_PCIE_1_PHY_BCR>,

				 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;

			reset-names = "phy", "nocsr";



			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;

			assigned-clock-rates = <100000000>;



			power-domains = <&gcc PCIE_1_PHY_GDSC>;



			#clock-cells = <0>;

			clock-output-names = "pcie1_pipe_clk";



			#phy-cells = <0>;



			status = "disabled";

		};



		cryptobam: dma-controller@1dc4000 {

			compatible = "qcom,bam-v1.7.0";

			reg = <0x0 0x01dc4000 0x0 0x28000>;