Commit 7d41e24d authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-x86-misc-6.10' of https://github.com/kvm-x86/linux into HEAD 

KVM x86 misc changes for 6.10:

 - Advertise the max mappable GPA in the "guest MAXPHYADDR" CPUID field, which
   is unused by hardware, so that KVM can communicate its inability to map GPAs
   that set bits 51:48 due to lack of 5-level paging.  Guest firmware is
   expected to use the information to safely remap BARs in the uppermost GPA
   space, i.e to avoid placing a BAR at a legal, but unmappable, GPA.

 - Use vfree() instead of kvfree() for allocations that always use vcalloc()
   or __vcalloc().

 - Don't completely ignore same-value writes to immutable feature MSRs, as
   doing so results in KVM failing to reject accesses to MSR that aren't
   supposed to exist given the vCPU model and/or KVM configuration.

 - Don't mark APICv as being inhibited due to ABSENT if APICv is disabled
   KVM-wide to avoid confusing debuggers (KVM will never bother clearing the
   ABSENT inhibit, even if userspace enables in-kernel local APIC).
parents 5a1c72e0 51937f2a

arch/x86/kvm/cpuid.c

+31 −10
Original line number Diff line number Diff line
@@ -1232,9 +1232,22 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 
		entry->eax = entry->ebx = entry->ecx = 0;

		break;

	case 0x80000008: {

		unsigned g_phys_as = (entry->eax >> 16) & 0xff;

		unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);

		unsigned phys_as = entry->eax & 0xff;

		/*

		 * GuestPhysAddrSize (EAX[23:16]) is intended for software

		 * use.

		 *

		 * KVM's ABI is to report the effective MAXPHYADDR for the

		 * guest in PhysAddrSize (phys_as), and the maximum

		 * *addressable* GPA in GuestPhysAddrSize (g_phys_as).

		 *

		 * GuestPhysAddrSize is valid if and only if TDP is enabled,

		 * in which case the max GPA that can be addressed by KVM may

		 * be less than the max GPA that can be legally generated by

		 * the guest, e.g. if MAXPHYADDR>48 but the CPU doesn't

		 * support 5-level TDP.

		 */

		unsigned int virt_as = max((entry->eax >> 8) & 0xff, 48U);

		unsigned int phys_as, g_phys_as;



		/*

		 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
@@ -1242,16 +1255,24 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 
		 * reductions in MAXPHYADDR for memory encryption affect shadow

		 * paging, too.

		 *

		 * If TDP is enabled but an explicit guest MAXPHYADDR is not

		 * provided, use the raw bare metal MAXPHYADDR as reductions to

		 * the HPAs do not affect GPAs.

		 * If TDP is enabled, use the raw bare metal MAXPHYADDR as

		 * reductions to the HPAs do not affect GPAs.  The max

		 * addressable GPA is the same as the max effective GPA, except

		 * that it's capped at 48 bits if 5-level TDP isn't supported

		 * (hardware processes bits 51:48 only when walking the fifth

		 * level page table).

		 */

		if (!tdp_enabled)

			g_phys_as = boot_cpu_data.x86_phys_bits;

		else if (!g_phys_as)

		if (!tdp_enabled) {

			phys_as = boot_cpu_data.x86_phys_bits;

			g_phys_as = 0;

		} else {

			phys_as = entry->eax & 0xff;

			g_phys_as = phys_as;

			if (kvm_mmu_get_max_tdp_level() < 5)

				g_phys_as = min(g_phys_as, 48);

		}



		entry->eax = g_phys_as | (virt_as << 8);

		entry->eax = phys_as | (virt_as << 8) | (g_phys_as << 16);

		entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));

		entry->edx = 0;

		cpuid_entry_override(entry, CPUID_8000_0008_EBX);

arch/x86/kvm/mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -100,6 +100,8 @@ static inline u8 kvm_get_shadow_phys_bits(void) 
	return boot_cpu_data.x86_phys_bits;

}



u8 kvm_mmu_get_max_tdp_level(void);



void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);

void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);

void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);

arch/x86/kvm/mmu/mmu.c

+5 −0
Original line number Diff line number Diff line
@@ -5316,6 +5316,11 @@ static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) 
	return max_tdp_level;

}



u8 kvm_mmu_get_max_tdp_level(void)

{

	return tdp_root_level ? tdp_root_level : max_tdp_level;

}



static union kvm_mmu_page_role

kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,

				union kvm_cpu_role cpu_role)

arch/x86/kvm/mmu/page_track.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ bool kvm_page_track_write_tracking_enabled(struct kvm *kvm) 


void kvm_page_track_free_memslot(struct kvm_memory_slot *slot)

{

	kvfree(slot->arch.gfn_write_track);

	vfree(slot->arch.gfn_write_track);

	slot->arch.gfn_write_track = NULL;

}

arch/x86/kvm/trace.h

+2 −2
Original line number Diff line number Diff line
@@ -1074,7 +1074,7 @@ TRACE_EVENT(kvm_smm_transition, 
);



/*

 * Tracepoint for VT-d posted-interrupts.

 * Tracepoint for VT-d posted-interrupts and AMD-Vi Guest Virtual APIC.

 */

TRACE_EVENT(kvm_pi_irte_update,

	TP_PROTO(unsigned int host_irq, unsigned int vcpu_id,
@@ -1100,7 +1100,7 @@ TRACE_EVENT(kvm_pi_irte_update, 
		__entry->set		= set;

	),



	TP_printk("VT-d PI is %s for irq %u, vcpu %u, gsi: 0x%x, "

	TP_printk("PI is %s for irq %u, vcpu %u, gsi: 0x%x, "

		  "gvec: 0x%x, pi_desc_addr: 0x%llx",

		  __entry->set ? "enabled and being updated" : "disabled",

		  __entry->host_irq,