Commit 7d5a7cc7 authored by Christopher Bednarz's avatar Christopher Bednarz Committed by Leon Romanovsky
Browse files

RDMA/irdma: Discover and set up GEN3 hardware register layout 



Discover the hardware register layout for GEN3 devices through an RDMA
virtual channel operation with the Control Plane (CP). Set up the
corresponding hardware attributes specific to GEN3 devices.

Signed-off-by: default avatarChristopher Bednarz <christopher.n.bednarz@intel.com>
Signed-off-by: default avatarTatyana Nikolova <tatyana.e.nikolova@intel.com>
Link: https://patch.msgid.link/20250827152545.2056-4-tatyana.e.nikolova@intel.com


Tested-by: default avatarJacob Moroni <jmoroni@google.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent d5edd333

drivers/infiniband/hw/irdma/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ irdma-objs := cm.o \ 
	      ig3rdma_if.o\

	      icrdma_if.o \

              icrdma_hw.o \

	      ig3rdma_hw.o\

              main.o      \

              pble.o      \

              puda.o      \

drivers/infiniband/hw/irdma/ctrl.c

+21 −10
Original line number Diff line number Diff line
@@ -5672,6 +5672,9 @@ static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) 
	case IRDMA_GEN_2:

		icrdma_init_hw(dev);

		break;

	case IRDMA_GEN_3:

		ig3rdma_init_hw(dev);

		break;

	}

}
@@ -5742,18 +5745,26 @@ int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev, 


	irdma_sc_init_hw(dev);



	if (dev->privileged) {

		if (irdma_wait_pe_ready(dev))

			return -ETIMEDOUT;



		val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);

		db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);

	if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {

		if (db_size != IRDMA_PE_DB_SIZE_4M &&

		    db_size != IRDMA_PE_DB_SIZE_8M) {

			ibdev_dbg(to_ibdev(dev),

				  "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",

				  val, db_size);

			return -ENODEV;

			}

	dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET];

	} else {

		ret_code = irdma_vchnl_req_get_reg_layout(dev);

		if (ret_code)

			ibdev_dbg(to_ibdev(dev),

				  "DEV: Get Register layout failed ret = %d\n",

				  ret_code);

	}



	return ret_code;

}

drivers/infiniband/hw/irdma/defs.h

+9 −3
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ enum irdma_protocol_used { 
#define IRDMA_FEATURE_BUF_SIZE		(8 * IRDMA_MAX_FEATURES)



#define ENABLE_LOC_MEM			63

#define IRDMA_ATOMICS_ALLOWED_BIT	1

#define MAX_PBLE_PER_SD			0x40000

#define MAX_PBLE_SD_PER_FCN		0x400

#define MAX_MR_PER_SD			0x8000
@@ -127,7 +128,7 @@ enum irdma_protocol_used { 
#define IRDMA_QP_SW_MAX_RQ_QUANTA	32768

#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \

	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))



#define IRDMA_SRQ_MAX_QUANTA 262144

#define IRDMAQP_TERM_SEND_TERM_AND_FIN		0

#define IRDMAQP_TERM_SEND_TERM_ONLY		1

#define IRDMAQP_TERM_SEND_FIN_ONLY		2
@@ -153,8 +154,13 @@ enum irdma_protocol_used { 
#define IRDMA_SQ_RSVD	258

#define IRDMA_RQ_RSVD	1



#define IRDMA_FEATURE_RTS_AE			1ULL

#define IRDMA_FEATURE_CQ_RESIZE			2ULL

#define IRDMA_FEATURE_RTS_AE			BIT_ULL(0)

#define IRDMA_FEATURE_CQ_RESIZE			BIT_ULL(1)

#define IRDMA_FEATURE_64_BYTE_CQE		BIT_ULL(5)

#define IRDMA_FEATURE_ATOMIC_OPS		BIT_ULL(6)

#define IRDMA_FEATURE_SRQ			BIT_ULL(7)

#define IRDMA_FEATURE_CQE_TIMESTAMPING		BIT_ULL(8)



#define IRDMAQP_OP_RDMA_WRITE			0x00

#define IRDMAQP_OP_RDMA_READ			0x01

#define IRDMAQP_OP_RDMA_SEND			0x03

drivers/infiniband/hw/irdma/i40iw_hw.c

+2 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ static u64 i40iw_masks[IRDMA_MAX_MASKS] = { 
	I40E_CQPSQ_CQ_CEQID,

	I40E_CQPSQ_CQ_CQID,

	I40E_COMMIT_FPM_CQCNT,

	I40E_CQPSQ_UPESD_HMCFNID,

};



static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = {
@@ -94,6 +95,7 @@ static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = { 
	I40E_CQPSQ_CQ_CEQID_S,

	I40E_CQPSQ_CQ_CQID_S,

	I40E_COMMIT_FPM_CQCNT_S,

	I40E_CQPSQ_UPESD_HMCFNID_S,

};



/**

drivers/infiniband/hw/irdma/i40iw_hw.h

+2 −0
Original line number Diff line number Diff line
@@ -123,6 +123,8 @@ 
#define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)

#define I40E_COMMIT_FPM_CQCNT_S 0

#define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)

#define I40E_CQPSQ_UPESD_HMCFNID_S 0

#define I40E_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)



#define I40E_VSIQF_CTL(_VSI)             (0x0020D800 + ((_VSI) * 4))