Commit 7d7a9fc1 authored by Mihai Sain's avatar Mihai Sain Committed by Claudiu Beznea
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ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node



Add the Performance Monitoring Unit (PMU) node with the appropriate
compatible string and interrupt line so that perf and other
PMU-based tooling can function correctly on this SoC.

[root@SAMA7D65 ~]$ dmesg | grep -i pmu
[    1.487869] hw-perfevents: enabled with armv7_cortex_a7 PMU driver, 5 (8000000f) counters available

[root@SAMA7D65 ~]$ perf list hw
List of pre-defined events (to be used in -e or -M):

branch-instructions OR branches                    [Hardware event]
branch-misses                                      [Hardware event]
bus-cycles                                         [Hardware event]
cache-misses                                       [Hardware event]
cache-references                                   [Hardware event]
cpu-cycles OR cycles                               [Hardware event]
instructions                                       [Hardware event]

Signed-off-by: default avatarMihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20260324070927.1496-2-mihai.sain@microchip.com


[claudiu.beznea: keep nodes alphanumerically sorted]
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent c52f2944
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+5 −0
Original line number Diff line number Diff line
@@ -67,6 +67,11 @@ ns_sram: sram@100000 {
		#size-cells = <1>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		ranges;