Unverified Commit 7d887c0c authored by Frank Wunderlich's avatar Frank Wunderlich Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt7988: Add pinctrl support 



Add mt7988a pinctrl node.

Signed-off-by: default avatarFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 0b5b1c88

arch/arm64/boot/dts/mediatek/mt7988a.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <dt-bindings/clock/mediatek,mt7988-clk.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/pinctrl/mt65xx.h>



/ {

	compatible = "mediatek,mt7988a";
@@ -105,6 +106,59 @@ clock-controller@1001e000 { 
			#clock-cells = <1>;

		};



		pio: pinctrl@1001f000 {

			compatible = "mediatek,mt7988-pinctrl";

			reg = <0 0x1001f000 0 0x1000>,

			      <0 0x11c10000 0 0x1000>,

			      <0 0x11d00000 0 0x1000>,

			      <0 0x11d20000 0 0x1000>,

			      <0 0x11e00000 0 0x1000>,

			      <0 0x11f00000 0 0x1000>,

			      <0 0x1000b000 0 0x1000>;

			reg-names = "gpio", "iocfg_tr",

				    "iocfg_br", "iocfg_rb",

				    "iocfg_lb", "iocfg_tl", "eint";

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pio 0 0 84>;

			interrupt-controller;

			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-parent = <&gic>;

			#interrupt-cells = <2>;



			pcie0_pins: pcie0-pins {

				mux {

					function = "pcie";

					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",

						 "pcie_wake_n0_0";

				};

			};



			pcie1_pins: pcie1-pins {

				mux {

					function = "pcie";

					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",

						 "pcie_wake_n1_0";

				};

			};



			pcie2_pins: pcie2-pins {

				mux {

					function = "pcie";

					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",

						 "pcie_wake_n2_0";

				};

			};



			pcie3_pins: pcie3-pins {

				mux {

					function = "pcie";

					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",

						 "pcie_wake_n3_0";

				};

			};

		};



		pwm@10048000 {

			compatible = "mediatek,mt7988-pwm";

			reg = <0 0x10048000 0 0x1000>;