Commit 7da6a357 authored by Prathamesh Shete's avatar Prathamesh Shete Committed by Linus Walleij
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pinctrl-tegra: Add config property GPIO mode 



The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing
system:
- When set to 1, the pin operates in SFIO mode, controlled by the
  pin's assigned special function.
- When set to 0, the pin operates as a general-purpose GPIO.

This SFIO/GPIO select bit that is set for a given pin is not displayed,
adding the support to retrieve this information from the
pinmux set for each pin.

Signed-off-by: default avatarPrathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/20241217153249.5712-1-pshete@nvidia.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent e2a9df2f

drivers/pinctrl/tegra/pinctrl-tegra.c

+11 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ static const struct cfg_param { 
	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},

	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},

	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},

	{"nvidia,gpio-mode",		TEGRA_PINCONF_PARAM_GPIO_MODE},

};



static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
@@ -468,6 +469,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, 
		*bit = g->drvtype_bit;

		*width = 2;

		break;

	case TEGRA_PINCONF_PARAM_GPIO_MODE:

		if (pmx->soc->sfsel_in_mux) {

			*bank = g->mux_bank;

			*reg = g->mux_reg;

			*bit = g->sfsel_bit;

			*width = 1;

		} else {

			*reg = -EINVAL;

		}

		break;

	default:

		dev_err(pmx->dev, "Invalid config param %04x\n", param);

		return -ENOTSUPP;

drivers/pinctrl/tegra/pinctrl-tegra.h

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,8 @@ enum tegra_pinconf_param { 
	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,

	/* argument: Integer, range is HW-dependant */

	TEGRA_PINCONF_PARAM_DRIVE_TYPE,

	/* argument: Boolean */

	TEGRA_PINCONF_PARAM_GPIO_MODE,

};



enum tegra_pinconf_pull {