Unverified Commit 7db4c4cd authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Mark Brown
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ASoC: codecs: lpass-wsa-macro: make use of snd_soc_component_read_field() 



Make use of snd_soc_component_read_field() to make the code more readable!

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20210126171749.1863-2-srinivas.kandagatla@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1da0b989

sound/soc/codecs/lpass-wsa-macro.c

+20 −23
Original line number Diff line number Diff line
@@ -40,9 +40,11 @@ 
#define CDC_WSA_TOP_I2S_CLK			(0x00A4)

#define CDC_WSA_TOP_I2S_RESET			(0x00A8)

#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0		(0x0100)

#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK	GENMASK(5, 3)

#define CDC_WSA_RX_INTX_2_SEL_MASK		GENMASK(2, 0)

#define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK	GENMASK(2, 0)

#define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK	GENMASK(5, 3)

#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1		(0x0104)

#define CDC_WSA_RX_INTX_2_SEL_MASK		GENMASK(2, 0)

#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK	GENMASK(5, 3)

#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0		(0x0108)

#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1		(0x010C)

#define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0		(0x0110)
@@ -229,8 +231,6 @@ 
#define NUM_INTERPOLATORS 2

#define WSA_NUM_CLKS_MAX	5

#define WSA_MACRO_MCLK_FREQ 19200000

#define WSA_MACRO_MUX_INP_SHFT 0x3

#define WSA_MACRO_MUX_INP_MASK1 0x07

#define WSA_MACRO_MUX_INP_MASK2 0x38

#define WSA_MACRO_MUX_CFG_OFFSET 0x8

#define WSA_MACRO_MUX_CFG1_OFFSET 0x4
@@ -843,7 +843,6 @@ static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 
	u32 j, port;

	u16 int_mux_cfg0, int_mux_cfg1;

	u16 int_fs_reg;

	u8 int_mux_cfg0_val, int_mux_cfg1_val;

	u8 inp0_sel, inp1_sel, inp2_sel;

	struct snd_soc_component *component = dai->component;

	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
@@ -865,15 +864,13 @@ static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 
		 */

		for (j = 0; j < NUM_INTERPOLATORS; j++) {

			int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;

			int_mux_cfg0_val = snd_soc_component_read(component,

								  int_mux_cfg0);

			int_mux_cfg1_val = snd_soc_component_read(component,

								  int_mux_cfg1);

			inp0_sel = int_mux_cfg0_val & WSA_MACRO_MUX_INP_MASK1;

			inp1_sel = (int_mux_cfg0_val >> WSA_MACRO_MUX_INP_SHFT) &

						WSA_MACRO_MUX_INP_MASK1;

			inp2_sel = (int_mux_cfg1_val >> WSA_MACRO_MUX_INP_SHFT) &

						WSA_MACRO_MUX_INP_MASK1;

			inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 

								CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);

			inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 

								CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);

			inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,

								CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);



			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||

			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||

			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
@@ -912,9 +909,9 @@ static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 


		int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;

		for (j = 0; j < NUM_INTERPOLATORS; j++) {

			int_mux_cfg1_val = snd_soc_component_read(component,

							int_mux_cfg1) &

							WSA_MACRO_MUX_INP_MASK1;

			int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,

									CDC_WSA_RX_INTX_2_SEL_MASK);



			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {

				int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +

					WSA_MACRO_RX_PATH_OFFSET * j;
@@ -1410,25 +1407,25 @@ static bool wsa_macro_adie_lb(struct snd_soc_component *component, 
			      int interp_idx)

{

	u16 int_mux_cfg0,  int_mux_cfg1;

	u8 int_mux_cfg0_val, int_mux_cfg1_val;

	u8 int_n_inp0, int_n_inp1, int_n_inp2;



	int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;

	int_mux_cfg1 = int_mux_cfg0 + 4;

	int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);

	int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);



	int_n_inp0 = int_mux_cfg0_val & 0x0F;

	int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,

						  CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);

	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||

		int_n_inp0 == INTn_1_INP_SEL_DEC1)

		return true;



	int_n_inp1 = int_mux_cfg0_val >> 4;

	int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,

						  CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);

	if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||

		int_n_inp1 == INTn_1_INP_SEL_DEC1)

		return true;



	int_n_inp2 = int_mux_cfg1_val >> 4;

	int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,

						  CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);

	if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||

		int_n_inp2 == INTn_1_INP_SEL_DEC1)

		return true;