Commit 7dc9b92d authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/xe: Remove i915_utils dependency from xe_pcode. 



Expand xe_mmio_wait32 to accept atomic and then use
that directly when possible, and create own routine to
wait for the pcode status.

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
parent 81593af6

drivers/gpu/drm/xe/xe_force_wake.c

+2 −2
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ static int domain_wake_wait(struct xe_gt *gt, 
{

	return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,

			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,

			      NULL);

			      NULL, false);

}



static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -138,7 +138,7 @@ static int domain_sleep_wait(struct xe_gt *gt, 
{

	return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,

			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,

			      NULL);

			      NULL, false);

}



#define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \

drivers/gpu/drm/xe/xe_gt.c

+1 −1
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ int do_gt_reset(struct xe_gt *gt) 


	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);

	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,

			     NULL);

			     NULL, false);

	if (err)

		drm_err(&xe->drm,

			"GT reset failed to clear GEN11_GRDOM_FULL\n");

drivers/gpu/drm/xe/xe_gt_mcr.c

+2 −1
Original line number Diff line number Diff line
@@ -376,7 +376,8 @@ static void mcr_lock(struct xe_gt *gt) 
	 * shares the same steering control register.

	 */

	if (GRAPHICS_VERx100(xe) >= 1270)

		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL);

		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL,

				     false);



	drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);

}

drivers/gpu/drm/xe/xe_guc.c

+5 −4
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ int xe_guc_reset(struct xe_guc *guc) 
	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);



	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,

			     &gdrst);

			     &gdrst, false);

	if (ret) {

		drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",

			gdrst);
@@ -423,7 +423,7 @@ static int guc_wait_ucode(struct xe_guc *guc) 
	ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,

			     FIELD_PREP(GS_UKERNEL_MASK,

					XE_GUC_LOAD_STATUS_READY),

			     GS_UKERNEL_MASK, 200000, &status);

			     GS_UKERNEL_MASK, 200000, &status, false);



	if (ret) {

		struct drm_device *drm = &xe->drm;
@@ -671,7 +671,7 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len) 
	ret = xe_mmio_wait32(gt, reply_reg,

			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,

					GUC_HXG_ORIGIN_GUC),

			     GUC_HXG_MSG_0_ORIGIN, 50000, &reply);

			     GUC_HXG_MSG_0_ORIGIN, 50000, &reply, false);

	if (ret) {

timeout:

		drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
@@ -686,7 +686,8 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len) 
		ret = xe_mmio_wait32(gt, reply_reg,

				     FIELD_PREP(GUC_HXG_MSG_0_TYPE,

						GUC_HXG_TYPE_RESPONSE_SUCCESS),

				     GUC_HXG_MSG_0_TYPE, 1000000, &header);

				     GUC_HXG_MSG_0_TYPE, 1000000, &header,

				     false);



		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=

			     GUC_HXG_ORIGIN_GUC))

drivers/gpu/drm/xe/xe_huc.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc) 


	ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,

			     HUC_LOAD_SUCCESSFUL,

			     HUC_LOAD_SUCCESSFUL, 100000, NULL);

			     HUC_LOAD_SUCCESSFUL, 100000, NULL, false);

	if (ret) {

		drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);

		goto fail;