Commit 7e459c41 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
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drm/msm/a8xx: Fix ubwc config related to swizzling 



To disable l2/l3 swizzling in A8x, set the respective bits in both
GRAS_NC_MODE_CNTL and RB_CCU_NC_MODE_CNTL registers. This is required
for Glymur where it is recommended to keep l2/l3 swizzling disabled.

Fixes: 288a9320 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Message-ID: <20260305-a8xx-ubwc-fix-v1-1-d99b6da4c5a9@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent e4eb6e4d

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

+12 −2
Original line number Diff line number Diff line
@@ -310,11 +310,21 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) 
	hbb = cfg->highest_bank_bit - 13;

	hbb_hi = hbb >> 2;

	hbb_lo = hbb & 3;

	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5);

	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, hbb << 5);



	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL,

			hbb << 5 |

			level3_swizzling_dis << 4 |

			level2_swizzling_dis << 3);



	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL,

			hbb << 5 |

			level3_swizzling_dis << 4 |

			level2_swizzling_dis << 3);



	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL,

			yuvnotcomptofc << 6 |

			level3_swizzling_dis << 5 |

			level2_swizzling_dis << 4 |

			hbb_hi << 3 |

			hbb_lo << 1);