Commit 7e515866 authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Joerg Roedel
Browse files

iommu/amd: Correct the reported page sizes from the V1 table 



The HW only has 52 bits of physical address support, the supported page
sizes should not have bits set beyond this. Further the spec says that the
6th level does not support any "default page size for translation entries"
meaning leafs in the 6th level are not allowed too.

Rework the definition to use GENMASK to build the range of supported pages
from the top of physical to 4k.

Nothing ever uses such large pages, so this is a cosmetic/documentation
improvement only.

Reported-by: default avatarJoao Martins <joao.m.martins@oracle.com>
Reviewed-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/13-v2-831cdc4d00f3+1a315-amd_iopgtbl_jgg@nvidia.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent c435209f

drivers/iommu/amd/amd_iommu_types.h

+2 −1
Original line number Diff line number Diff line
@@ -290,8 +290,9 @@ 
 * that we support.

 *

 * 512GB Pages are not supported due to a hardware bug

 * Page sizes >= the 52 bit max physical address of the CPU are not supported.

 */

#define AMD_IOMMU_PGSIZES	((~0xFFFUL) & ~(2ULL << 38))

#define AMD_IOMMU_PGSIZES	(GENMASK_ULL(51, 12) ^ SZ_512G)

/* 4K, 2MB, 1G page sizes are supported */

#define AMD_IOMMU_PGSIZES_V2	(PAGE_SIZE | (1ULL << 21) | (1ULL << 30))