Commit 7e757092 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D 



All the places that use DSPCLK_GATE_D are specific to certain platforms,
and the parametrization of it to support VLV/CHV MMIO display base isn't
really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D
and use it.

Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/ac16d9d5192595944bf9bcf70aa721b504bc90c0.1754499175.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 85cac9ff

drivers/gpu/drm/i915/display/intel_display_power_well.c

+1 −1
Original line number Diff line number Diff line
@@ -1209,7 +1209,7 @@ static void vlv_init_display_clock_gating(struct intel_display *display) 
	 * (and never recovering) in this case. intel_dsi_post_disable() will

	 * clear it when we turn off the display.

	 */

	intel_de_rmw(display, DSPCLK_GATE_D(display),

	intel_de_rmw(display, VLV_DSPCLK_GATE_D,

		     ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);



	/*

drivers/gpu/drm/i915/display/intel_gmbus.c

+1 −1
Original line number Diff line number Diff line
@@ -219,7 +219,7 @@ static void pnv_gmbus_clock_gating(struct intel_display *display, 
				   bool enable)

{

	/* When using bit bashing for I2C, this bit needs to be set to 1 */

	intel_de_rmw(display, DSPCLK_GATE_D(display),

	intel_de_rmw(display, DSPCLK_GATE_D,

		     PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,

		     !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);

}

drivers/gpu/drm/i915/display/intel_overlay.c

+2 −3
Original line number Diff line number Diff line
@@ -217,10 +217,9 @@ static void i830_overlay_clock_gating(struct intel_display *display, 


	/* WA_OVERLAY_CLKGATE:alm */

	if (enable)

		intel_de_write(display, DSPCLK_GATE_D(display), 0);

		intel_de_write(display, DSPCLK_GATE_D, 0);

	else

		intel_de_write(display, DSPCLK_GATE_D(display),

			       OVRUNIT_CLOCK_GATE_DISABLE);

		intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);



	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */

	pci_bus_read_config_byte(pdev->bus,

drivers/gpu/drm/i915/display/vlv_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -761,7 +761,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, 


	if (display->platform.valleyview || display->platform.cherryview) {

		/* Disable DPOunit clock gating, can stall pipe */

		intel_de_rmw(display, DSPCLK_GATE_D(display),

		intel_de_rmw(display, VLV_DSPCLK_GATE_D,

			     0, DPOUNIT_CLOCK_GATE_DISABLE);

	}
@@ -918,7 +918,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, 
	} else {

		vlv_dsi_pll_disable(encoder);



		intel_de_rmw(display, DSPCLK_GATE_D(display),

		intel_de_rmw(display, VLV_DSPCLK_GATE_D,

			     DPOUNIT_CLOCK_GATE_DISABLE, 0);

	}

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -613,7 +613,8 @@ 
#define  DSTATE_GFX_CLOCK_GATING		(1 << 1)

#define  DSTATE_DOT_CLOCK_GATING		(1 << 0)



#define DSPCLK_GATE_D(__i915)		_MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)

#define DSPCLK_GATE_D			_MMIO(0x6200)

#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)

# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */

# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */

# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */