Commit 7ead14d4 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: offset HBB values written to DPU by -13 



As in all other places, the Highest Bank Bit value should be programmed
into the hardware with the offset of -13.  Correct the value written
into the register to prevent unpredictable results.

Fixes: 227d4ce0 ("drm/msm: Offset MDSS HBB value by 13")
Tested-by: Val Packett <val@packett.cool> # x1e80100-dell-latitude-7455
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/699276/
Link: https://lore.kernel.org/r/20260119-msm-ubwc-fixes-v4-2-0987acc0427f@oss.qualcomm.com
parent e6177c7a

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

+6 −4
Original line number Diff line number Diff line
@@ -270,30 +270,32 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, 
		((fmt->bpp - 1) << 9);



	if (fmt->fetch_mode != MDP_FETCH_LINEAR) {

		u32 hbb = ctx->ubwc->highest_bank_bit - 13;



		if (MSM_FORMAT_IS_UBWC(fmt))

			opmode |= MDSS_MDP_OP_BWC_EN;

		src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */

		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,

			DPU_FETCH_CONFIG_RESET_VALUE |

			ctx->ubwc->highest_bank_bit << 18);

			hbb << 18);

		switch (ctx->ubwc->ubwc_enc_version) {

		case UBWC_1_0:

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |

					BIT(8) |

					(ctx->ubwc->highest_bank_bit << 4));

					(hbb << 4));

			break;

		case UBWC_2_0:

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					fast_clear | (ctx->ubwc->ubwc_swizzle) |

					(ctx->ubwc->highest_bank_bit << 4));

					(hbb << 4));

			break;

		case UBWC_3_0:

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					BIT(30) | (ctx->ubwc->ubwc_swizzle) |

					(ctx->ubwc->highest_bank_bit << 4));

					(hbb << 4));

			break;

		case UBWC_4_0:

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,