Commit 7eb90295 authored by Petr Machata's avatar Petr Machata Committed by Jakub Kicinski
Browse files

mlxsw: reg: Mark SFGC & some SFMR fields as reserved in CFF mode 



Some existing fields and the whole register of SFGC are reserved in CFF
mode. Backport the reservation note to these fields.

Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
Reviewed-by: default avatarAmit Cohen <amcohen@nvidia.com>
Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/e1d5977a8cb778227e4ea2fd1515529957ce5de7.1700503643.git.petrm@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent e1e4ce6c

drivers/net/ethernet/mellanox/mlxsw/reg.h

+6 −0
Original line number Diff line number Diff line
@@ -1024,6 +1024,8 @@ static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 
 * ------------------------------------------

 * The following register controls the association of flooding tables and MIDs

 * to packet types used for flooding.

 *

 * Reserved when CONFIG_PROFILE.flood_mode = CFF.

 */

#define MLXSW_REG_SFGC_ID 0x2011

#define MLXSW_REG_SFGC_LEN 0x14
@@ -1862,6 +1864,7 @@ MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 
 * Access: RW

 *

 * Note: Reserved when legacy bridge model is used.

 * Reserved when CONFIG_PROFILE.flood_mode = CFF.

 */

MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
@@ -1872,6 +1875,7 @@ MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 
 * Access: RW

 *

 * Note: Reserved when legacy bridge model is used and when flood_rsp=1.

 * Reserved when CONFIG_PROFILE.flood_mode = CFF

 */

MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
@@ -1880,6 +1884,8 @@ MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 
 * Used to point into the flooding table selected by SFGC register if

 * the table is of type FID-Offset. Otherwise, this field is reserved.

 * Access: RW

 *

 * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF

 */

MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);