Commit 7ed3c77a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

Merge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-dts-for-v6.16 

Renesas RZ/V2N DT Bindings and Definitions

DT bindings and binding definitions for the Renesas RZ/V2N (R9A09G056)
SoC, shared by driver and DT source files.
parents dc40879d 626acded

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+3 −2
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@@ -4,13 +4,13 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.
@@ -19,6 +19,7 @@ properties: 
  compatible:

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g056-cpg # RZ/V2N

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

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@@ -27,6 +27,7 @@ properties: 
              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

              - renesas,r9a08g045-pinctrl # RZ/G3S

              - renesas,r9a09g047-pinctrl # RZ/G3E

              - renesas,r9a09g056-pinctrl # RZ/V2N

              - renesas,r9a09g057-pinctrl # RZ/V2H(P)



      - items:
@@ -145,6 +146,7 @@ allOf: 
          contains:

            enum:

              - renesas,r9a09g047-pinctrl

              - renesas,r9a09g056-pinctrl

              - renesas,r9a09g057-pinctrl

    then:

      properties:

Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml

+1 −0
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@@ -25,6 +25,7 @@ properties: 
    items:

      - enum:

          - renesas,r9a09g047-sys # RZ/G3E

          - renesas,r9a09g056-sys # RZ/V2N

          - renesas,r9a09g057-sys # RZ/V2H



  reg:

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

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@@ -551,6 +551,21 @@ properties: 
              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2N (R9A09G056)

        items:

          - enum:

              - renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)

          - enum:

              - renesas,r9a09g056n41 # RZ/V2N

              - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support

              - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support

              - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support

              - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support

              - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support

              - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support

              - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support

          - const: renesas,r9a09g056



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

include/dt-bindings/clock/renesas,r9a09g056-cpg.h

0 → 100644
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

 *

 * Copyright (C) 2025 Renesas Electronics Corp.

 */

#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__

#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__



#include <dt-bindings/clock/renesas-cpg-mssr.h>



/* Core Clock list */

#define R9A09G056_SYS_0_PCLK			0

#define R9A09G056_CA55_0_CORE_CLK0		1

#define R9A09G056_CA55_0_CORE_CLK1		2

#define R9A09G056_CA55_0_CORE_CLK2		3

#define R9A09G056_CA55_0_CORE_CLK3		4

#define R9A09G056_CA55_0_PERIPHCLK		5

#define R9A09G056_CM33_CLK0			6

#define R9A09G056_CST_0_SWCLKTCK		7

#define R9A09G056_IOTOP_0_SHCLK			8

#define R9A09G056_USB2_0_CLK_CORE0		9

#define R9A09G056_GBETH_0_CLK_PTP_REF_I		10

#define R9A09G056_GBETH_1_CLK_PTP_REF_I		11



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */