Commit 7ee983c8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Just regular drm fixes, amdgpu, xe and i915 mostly, but a few
  scattered fixes. I think one of the i915 fixes fixes some build combos
  that Guenter was seeing.

  amdgpu:
   - Add new tiling flag for DCC write compress disable
   - Add BO metadata flag for DCC
   - Fix potential out of bounds access in display
   - Seamless boot fix
   - CONFIG_FRAME_WARN fix
   - PSR1 fix

  xe:
   - OA uAPI related fixes
   - Fix SRIOV migration initialization
   - Restore devcoredump to a sane state

  i915:
   - Fix the build error with clamp after WARN_ON on gcc 13.x+
   - HDCP related fixes
   - PMU fix zero delta busyness issue
   - Fix page cleanup on DMA remap failure
   - Drop 64bpp YUV formats from ICL+ SDR planes
   - GuC log related fix
   - DisplayPort related fixes

  ivpu:
   - Fix error handling

  komeda:
   - add return check

  zynqmp:
   - fix locking in DP code

  ast:
   - fix AST DP timeout

  cec:
   - fix broken CEC adapter check"

* tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel: (29 commits)
  drm/i915/dp: Fix potential infinite loop in 128b/132b SST
  Revert "drm/amd/display: Use HW lock mgr for PSR1"
  drm/amd/display: Respect user's CONFIG_FRAME_WARN more for dml files
  accel/amdxdna: Add MODULE_FIRMWARE() declarations
  drm/i915/dp: Iterate DSC BPP from high to low on all platforms
  drm/xe: Fix and re-enable xe_print_blob_ascii85()
  drm/xe/devcoredump: Move exec queue snapshot to Contexts section
  drm/xe/oa: Set stream->pollin in xe_oa_buffer_check_unlocked
  drm/xe/pf: Fix migration initialization
  drm/xe/oa: Preserve oa_ctrl unused bits
  drm/amd/display: Fix seamless boot sequence
  drm/amd/display: Fix out-of-bound accesses
  drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan
  drm/i915/backlight: Return immediately when scale() finds invalid parameters
  drm/i915/dp: Return min bpc supported by source instead of 0
  drm/i915/dp: fix the Adaptive sync Operation mode for SDP
  drm/i915/guc: Debug print LRC state entries only if the context is pinned
  drm/i915: Drop 64bpp YUV formats from ICL+ SDR planes
  drm/i915: Fix page cleanup on DMA remap failure
  drm/i915/pmu: Fix zero delta busyness issue
  ...
parents 8aa0f49c 4f6993b3

drivers/accel/amdxdna/amdxdna_pci_drv.c

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,11 @@ 


#define AMDXDNA_AUTOSUSPEND_DELAY	5000 /* milliseconds */



MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");

MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");

MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");

MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");



/*

 * Bind the driver base on (vendor_id, device_id) pair and later use the

 * (device_id, rev_id) pair as a key to select the devices. The devices with

drivers/accel/ivpu/ivpu_drv.c

+6 −2
Original line number Diff line number Diff line
@@ -397,15 +397,19 @@ int ivpu_boot(struct ivpu_device *vdev) 
	if (ivpu_fw_is_cold_boot(vdev)) {

		ret = ivpu_pm_dct_init(vdev);

		if (ret)

			goto err_diagnose_failure;

			goto err_disable_ipc;



		ret = ivpu_hw_sched_init(vdev);

		if (ret)

			goto err_diagnose_failure;

			goto err_disable_ipc;

	}



	return 0;



err_disable_ipc:

	ivpu_ipc_disable(vdev);

	ivpu_hw_irq_disable(vdev);

	disable_irq(vdev->irq);

err_diagnose_failure:

	ivpu_hw_diagnose_failure(vdev);

	ivpu_mmu_evtq_dump(vdev);

drivers/accel/ivpu/ivpu_pm.c

+47 −37
Original line number Diff line number Diff line
@@ -115,41 +115,57 @@ static int ivpu_resume(struct ivpu_device *vdev) 
	return ret;

}



static void ivpu_pm_recovery_work(struct work_struct *work)

static void ivpu_pm_reset_begin(struct ivpu_device *vdev)

{

	struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);

	struct ivpu_device *vdev = pm->vdev;

	char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};

	int ret;



	ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));



	ret = pm_runtime_resume_and_get(vdev->drm.dev);

	if (ret)

		ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);



	ivpu_jsm_state_dump(vdev);

	ivpu_dev_coredump(vdev);

	pm_runtime_disable(vdev->drm.dev);



	atomic_inc(&vdev->pm->reset_counter);

	atomic_set(&vdev->pm->reset_pending, 1);

	down_write(&vdev->pm->reset_lock);

}



static void ivpu_pm_reset_complete(struct ivpu_device *vdev)

{

	int ret;



	ivpu_suspend(vdev);

	ivpu_pm_prepare_cold_boot(vdev);

	ivpu_jobs_abort_all(vdev);

	ivpu_ms_cleanup_all(vdev);



	ret = ivpu_resume(vdev);

	if (ret)

	if (ret) {

		ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);

		pm_runtime_set_suspended(vdev->drm.dev);

	} else {

		pm_runtime_set_active(vdev->drm.dev);

	}



	up_write(&vdev->pm->reset_lock);

	atomic_set(&vdev->pm->reset_pending, 0);



	kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);

	pm_runtime_mark_last_busy(vdev->drm.dev);

	pm_runtime_put_autosuspend(vdev->drm.dev);

	pm_runtime_enable(vdev->drm.dev);

}



static void ivpu_pm_recovery_work(struct work_struct *work)

{

	struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);

	struct ivpu_device *vdev = pm->vdev;

	char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};



	ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));



	ivpu_pm_reset_begin(vdev);



	if (!pm_runtime_status_suspended(vdev->drm.dev)) {

		ivpu_jsm_state_dump(vdev);

		ivpu_dev_coredump(vdev);

		ivpu_suspend(vdev);

	}



	ivpu_pm_reset_complete(vdev);



	kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);

}



void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
@@ -309,7 +325,10 @@ int ivpu_rpm_get(struct ivpu_device *vdev) 
	int ret;



	ret = pm_runtime_resume_and_get(vdev->drm.dev);

	drm_WARN_ON(&vdev->drm, ret < 0);

	if (ret < 0) {

		ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);

		pm_runtime_set_suspended(vdev->drm.dev);

	}



	return ret;

}
@@ -325,16 +344,13 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev) 
	struct ivpu_device *vdev = pci_get_drvdata(pdev);



	ivpu_dbg(vdev, PM, "Pre-reset..\n");

	atomic_inc(&vdev->pm->reset_counter);

	atomic_set(&vdev->pm->reset_pending, 1);



	pm_runtime_get_sync(vdev->drm.dev);

	down_write(&vdev->pm->reset_lock);

	ivpu_pm_reset_begin(vdev);



	if (!pm_runtime_status_suspended(vdev->drm.dev)) {

		ivpu_prepare_for_reset(vdev);

		ivpu_hw_reset(vdev);

	ivpu_pm_prepare_cold_boot(vdev);

	ivpu_jobs_abort_all(vdev);

	ivpu_ms_cleanup_all(vdev);

	}



	ivpu_dbg(vdev, PM, "Pre-reset done.\n");

}
@@ -342,18 +358,12 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev) 
void ivpu_pm_reset_done_cb(struct pci_dev *pdev)

{

	struct ivpu_device *vdev = pci_get_drvdata(pdev);

	int ret;



	ivpu_dbg(vdev, PM, "Post-reset..\n");

	ret = ivpu_resume(vdev);

	if (ret)

		ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);

	up_write(&vdev->pm->reset_lock);

	atomic_set(&vdev->pm->reset_pending, 0);

	ivpu_dbg(vdev, PM, "Post-reset done.\n");



	pm_runtime_mark_last_busy(vdev->drm.dev);

	pm_runtime_put_autosuspend(vdev->drm.dev);

	ivpu_pm_reset_complete(vdev);



	ivpu_dbg(vdev, PM, "Post-reset done.\n");

}



void ivpu_pm_init(struct ivpu_device *vdev)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -119,9 +119,10 @@ 
 * - 3.57.0 - Compute tunneling on GFX10+

 * - 3.58.0 - Add GFX12 DCC support

 * - 3.59.0 - Cleared VRAM

 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	59

#define KMS_DRIVER_MINOR	60

#define KMS_DRIVER_PATCHLEVEL	0



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+6 −2
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 
	mutex_lock(&adev->mman.gtt_window_lock);

	while (src_mm.remaining) {

		uint64_t from, to, cur_size, tiling_flags;

		uint32_t num_type, data_format, max_com;

		uint32_t num_type, data_format, max_com, write_compress_disable;

		struct dma_fence *next;



		/* Never copy more than 256MiB at once to avoid a timeout */
@@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 
			max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

			num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);

			data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);

			write_compress_disable =

				AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);

			copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |

				       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |

				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));

				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |

				       AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,

							     write_compress_disable));

		}



		r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,