Commit 7f071dde authored by Clint Taylor's avatar Clint Taylor Committed by Radhakrishna Sripada
Browse files

drm/i915/bmg: Lane reversal requires writes to both context lanes 



Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.

v2: Update title(RK)
Bspec: 64539
CC: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarClint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-2-radhakrishna.sripada@intel.com
parent aa66c93d

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+5 −5
Original line number Diff line number Diff line
@@ -2337,7 +2337,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
{

	const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;

	bool dp = false;

	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;

	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

	u32 clock = crtc_state->port_clock;

	bool cntx;

	int i;
@@ -2402,19 +2402,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
	}



	/* 4. Program custom width to match the link protocol */

	intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH,

	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,

		      PHY_C20_CUSTOM_WIDTH_MASK,

		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)),

		      MB_WRITE_COMMITTED);



	/* 5. For DP or 6. For HDMI */

	if (dp) {

		intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,

		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,

			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),

			      MB_WRITE_COMMITTED);

	} else {

		intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,

		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,

			      is_hdmi_frl(clock) ? BIT(7) : 0,

			      MB_WRITE_COMMITTED);
@@ -2428,7 +2428,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, 
	 * 7. Write Vendor specific registers to toggle context setting to load

	 * the updated programming toggle context bit

	 */

	intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,

	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

		      BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);

}