Commit 7f1f78b9 authored by Sergey Matsievskiy's avatar Sergey Matsievskiy Committed by Thomas Gleixner
Browse files

irqchip/ocelot: Comment sticky register clearing code 



Add comment to the sticky register clearing code.

Signed-off-by: default avatarSergey Matsievskiy <matsievskiysv@gmail.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240925184416.54204-3-matsievskiysv@gmail.com
parent 9e9c4666

drivers/irqchip/irq-mscc-ocelot.c

+6 −0
Original line number Diff line number Diff line
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data) 
	u32 val;



	irq_gc_lock(gc);

	/*

	 * Clear sticky bits for edge mode interrupts.

	 * Serval has only one trigger register replication, but the adjacent

	 * register is always read as zero, so there's no need to handle this

	 * case separately.

	 */

	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |

		irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));

	if (!(val & mask))