Commit 7f9d82a0 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'fix-missing-phy-to-mac-rx-clock' 

Romain Gantois says:

====================
Fix missing PHY-to-MAC RX clock

There is an issue with some stmmac/PHY combinations that has been reported
some time ago in a couple of different series:

Clark Wang's report:
https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/
Clément Léger's report:
https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/

Stmmac controllers require an RX clock signal from the MII bus to perform
their hardware initialization successfully. This causes issues with some
PHY/PCS devices. If these devices do not bring the clock signal up before
the MAC driver initializes its hardware, then said initialization will
fail. This can happen at probe time or when the system wakes up from a
suspended state.

This series introduces new flags for phy_device and phylink_pcs. These
flags allow MAC drivers to signal to PHY/PCS drivers that the RX clock
signal should be enabled as soon as possible, and that it should always
stay enabled.

I have included specific uses of these flags that fix the RZN1 GMAC1 stmmac
driver that I am currently working on and that is not yet upstream. I have
also included changes to the at803x PHY driver that should fix the issue
that Clark Wang was having.
====================

Link: https://lore.kernel.org/r/20240326-rxc_bugfix-v6-0-24a74e5c761f@bootlin.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents af352c3b 0f671b3b

drivers/net/ethernet/stmicro/stmmac/common.h

+1 −1
Original line number Diff line number Diff line
@@ -593,7 +593,7 @@ struct mac_device_info { 
	const struct stmmac_mmc_ops *mmc;

	const struct stmmac_est_ops *est;

	struct dw_xpcs *xpcs;

	struct phylink_pcs *lynx_pcs; /* Lynx external PCS */

	struct phylink_pcs *phylink_pcs;

	struct mii_regs mii;	/* MII register Addresses */

	struct mac_link link;

	void __iomem *pcsr;     /* vpointer to device CSRs */

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

+4 −4
Original line number Diff line number Diff line
@@ -479,9 +479,9 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) 
			goto err_dvr_remove;

		}



		stpriv->hw->lynx_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);

		if (IS_ERR(stpriv->hw->lynx_pcs)) {

			ret = PTR_ERR(stpriv->hw->lynx_pcs);

		stpriv->hw->phylink_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);

		if (IS_ERR(stpriv->hw->phylink_pcs)) {

			ret = PTR_ERR(stpriv->hw->phylink_pcs);

			goto err_dvr_remove;

		}

	}
@@ -498,7 +498,7 @@ static void socfpga_dwmac_remove(struct platform_device *pdev) 
{

	struct net_device *ndev = platform_get_drvdata(pdev);

	struct stmmac_priv *priv = netdev_priv(ndev);

	struct phylink_pcs *pcs = priv->hw->lynx_pcs;

	struct phylink_pcs *pcs = priv->hw->phylink_pcs;



	stmmac_pltfr_remove(pdev);

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

+9 −6
Original line number Diff line number Diff line
@@ -944,10 +944,7 @@ static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 
	if (priv->hw->xpcs)

		return &priv->hw->xpcs->pcs;



	if (priv->hw->lynx_pcs)

		return priv->hw->lynx_pcs;



	return NULL;

	return priv->hw->phylink_pcs;

}



static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
@@ -1221,6 +1218,9 @@ static int stmmac_phy_setup(struct stmmac_priv *priv) 
	priv->phylink_config.type = PHYLINK_NETDEV;

	priv->phylink_config.mac_managed_pm = true;



	/* Stmmac always requires an RX clock for hardware initialization */

	priv->phylink_config.mac_requires_rxc = true;



	mdio_bus_data = priv->plat->mdio_bus_data;

	if (mdio_bus_data)

		priv->phylink_config.ovr_an_inband =
@@ -3411,6 +3411,10 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 
	u32 chan;

	int ret;



	/* Make sure RX clock is enabled */

	if (priv->hw->phylink_pcs)

		phylink_pcs_pre_init(priv->phylink, priv->hw->phylink_pcs);



	/* DMA initialization and SW reset */

	ret = stmmac_init_dma_engine(priv);

	if (ret < 0) {
@@ -3960,8 +3964,7 @@ static int __stmmac_open(struct net_device *dev, 
	if (priv->hw->pcs != STMMAC_PCS_TBI &&

	    priv->hw->pcs != STMMAC_PCS_RTBI &&

	    (!priv->hw->xpcs ||

	     xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) &&

	    !priv->hw->lynx_pcs) {

	     xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {

		ret = stmmac_init_phy(dev);

		if (ret) {

			netdev_err(priv->dev,

drivers/net/pcs/pcs-rzn1-miic.c

+28 −0
Original line number Diff line number Diff line
@@ -279,10 +279,38 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, 
	return -EINVAL;

}



static int miic_pre_init(struct phylink_pcs *pcs)

{

	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);

	struct miic *miic = miic_port->miic;

	u32 val, mask;



	/* Start RX clock if required */

	if (pcs->rxc_always_on) {

		/* In MII through mode, the clock signals will be driven by the

		 * external PHY, which might not be initialized yet. Set RMII

		 * as default mode to ensure that a reference clock signal is

		 * generated.

		 */

		miic_port->interface = PHY_INTERFACE_MODE_RMII;



		val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) |

		      FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS);

		mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED;



		miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val);



		miic_converter_enable(miic, miic_port->port, 1);

	}



	return 0;

}



static const struct phylink_pcs_ops miic_phylink_ops = {

	.pcs_validate = miic_validate,

	.pcs_config = miic_config,

	.pcs_link_up = miic_link_up,

	.pcs_pre_init = miic_pre_init,

};



struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)

drivers/net/phy/phylink.c

+24 −1
Original line number Diff line number Diff line
@@ -1042,6 +1042,21 @@ static void phylink_pcs_poll_start(struct phylink *pl) 
		mod_timer(&pl->link_poll, jiffies + HZ);

}



int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)

{

	int ret = 0;



	/* Signal to PCS driver that MAC requires RX clock for init */

	if (pl->config->mac_requires_rxc)

		pcs->rxc_always_on = true;



	if (pcs->ops->pcs_pre_init)

		ret = pcs->ops->pcs_pre_init(pcs);



	return ret;

}

EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);



static void phylink_mac_config(struct phylink *pl,

			       const struct phylink_link_state *state)

{
@@ -1923,6 +1938,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, 
static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy,

			      phy_interface_t interface)

{

	u32 flags = 0;



	if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED ||

		    (pl->cfg_link_an_mode == MLO_AN_INBAND &&

		     phy_interface_mode_is_8023z(interface) && !pl->sfp_bus)))
@@ -1931,7 +1948,10 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, 
	if (pl->phydev)

		return -EBUSY;



	return phy_attach_direct(pl->netdev, phy, 0, interface);

	if (pl->config->mac_requires_rxc)

		flags |= PHY_F_RXC_ALWAYS_ON;



	return phy_attach_direct(pl->netdev, phy, flags, interface);

}



/**
@@ -2034,6 +2054,9 @@ int phylink_fwnode_phy_connect(struct phylink *pl, 
		pl->link_config.interface = pl->link_interface;

	}



	if (pl->config->mac_requires_rxc)

		flags |= PHY_F_RXC_ALWAYS_ON;



	ret = phy_attach_direct(pl->netdev, phy_dev, flags,

				pl->link_interface);

	phy_device_free(phy_dev);