Commit 7fa5e292 authored by Isaku Yamahata's avatar Isaku Yamahata Committed by Paolo Bonzini
Browse files

KVM: x86/mmu: Add Suppress VE bit to EPT shadow_mmio_mask/shadow_present_mask 



To make use of the same value of shadow_mmio_mask and shadow_present_mask
for TDX and VMX, add Suppress-VE bit to shadow_mmio_mask and
shadow_present_mask so that they can be common for both VMX and TDX.

TDX will require shadow_mmio_mask and shadow_present_mask to include
VMX_SUPPRESS_VE for shared GPA so that EPT violation is triggered for
shared GPA.  For VMX, VMX_SUPPRESS_VE doesn't matter for MMIO because the
spte value is defined so as to cause EPT misconfig.

Signed-off-by: default avatarIsaku Yamahata <isaku.yamahata@intel.com>
Message-Id: <97cc616b3563cd8277be91aaeb3e14bce23c3649.1705965635.git.isaku.yamahata@intel.com>
Reviewed-by: default avatarXiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 7f01cab8

arch/x86/include/asm/vmx.h

+1 −0
Original line number Diff line number Diff line
@@ -514,6 +514,7 @@ enum vmcs_field { 
#define VMX_EPT_IPAT_BIT    			(1ull << 6)

#define VMX_EPT_ACCESS_BIT			(1ull << 8)

#define VMX_EPT_DIRTY_BIT			(1ull << 9)

#define VMX_EPT_SUPPRESS_VE_BIT			(1ull << 63)

#define VMX_EPT_RWX_MASK                        (VMX_EPT_READABLE_MASK |       \

						 VMX_EPT_WRITABLE_MASK |       \

						 VMX_EPT_EXECUTABLE_MASK)

arch/x86/kvm/mmu/spte.c

+4 −2
Original line number Diff line number Diff line
@@ -413,7 +413,9 @@ void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 
	shadow_dirty_mask	= has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;

	shadow_nx_mask		= 0ull;

	shadow_x_mask		= VMX_EPT_EXECUTABLE_MASK;

	shadow_present_mask	= has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;

	/* VMX_EPT_SUPPRESS_VE_BIT is needed for W or X violation. */

	shadow_present_mask	=

		(has_exec_only ? 0ull : VMX_EPT_READABLE_MASK) | VMX_EPT_SUPPRESS_VE_BIT;

	/*

	 * EPT overrides the host MTRRs, and so KVM must program the desired

	 * memtype directly into the SPTEs.  Note, this mask is just the mask
@@ -430,7 +432,7 @@ void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 
	 * of an EPT paging-structure entry is 110b (write/execute).

	 */

	kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,

				   VMX_EPT_RWX_MASK, 0);

				   VMX_EPT_RWX_MASK | VMX_EPT_SUPPRESS_VE_BIT, 0);

}

EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks);