Commit 7fcf7558 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/display: use intel_encoder_is/to_* functions 



Wherever possible, replace the port/phy based functions with the encoder
based functions:

intel_is_c10phy()	-> intel_encoder_is_c10phy()
intel_phy_is_combo()	-> intel_encoder_is_combo()
intel_phy_is_tc()	-> intel_encoder_is_tc()
intel_port_to_phy()	-> intel_encoder_to_phy()
intel_port_to_tc()	-> intel_encoder_to_tc()

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ce8d116fcdd7662fa0a0817200a8e6fda313e496.1710949619.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent ba28989d

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+11 −25
Original line number Diff line number Diff line
@@ -423,7 +423,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 
{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	const struct intel_ddi_buf_trans *trans;

	enum phy phy = intel_port_to_phy(i915, encoder->port);

	u8 owned_lane_mask;

	intel_wakeref_t wakeref;

	int n_entries, ln;
@@ -442,7 +441,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 
		return;

	}



	if (intel_is_c10phy(i915, phy)) {

	if (intel_encoder_is_c10phy(encoder)) {

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),

			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),
@@ -483,7 +482,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 
		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,

		      MB_WRITE_COMMITTED);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),

			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
@@ -2046,10 +2045,8 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock) 
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)

{

	struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);

	struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);

	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(&dig_port->base))

		return intel_c10_phy_check_hdmi_link_rate(clock);

	return intel_c20_phy_check_hdmi_link_rate(clock);

}
@@ -2097,10 +2094,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, 
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,

			    struct intel_encoder *encoder)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		return intel_c10pll_calc_state(crtc_state, encoder);

	return intel_c20pll_calc_state(crtc_state, encoder);

}
@@ -2652,7 +2646,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, 
	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);

	enum port port = encoder->port;



	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))

	if (intel_encoder_is_c10phy(encoder))

		intel_cx0_rmw(i915, port, owned_lane_mask,

			      PHY_C10_VDR_CONTROL(1), 0,

			      C10_VDR_CTRL_MSGBUS_ACCESS,
@@ -2681,7 +2675,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, 
			      MB_WRITE_COMMITTED);

	}



	if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))

	if (intel_encoder_is_c10phy(encoder))

		intel_cx0_rmw(i915, port, owned_lane_mask,

			      PHY_C10_VDR_CONTROL(1), 0,

			      C10_VDR_CTRL_UPDATE_CFG,
@@ -2744,7 +2738,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, 
	 */



	/* 5. Program PHY internal PLL internal registers. */

	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		intel_c10_pll_program(i915, crtc_state, encoder);

	else

		intel_c20_pll_program(i915, crtc_state, encoder);
@@ -2902,7 +2896,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) 
{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);

	bool is_c10 = intel_is_c10phy(i915, phy);

	bool is_c10 = intel_encoder_is_c10phy(encoder);

	intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);



	/* 1. Change owned PHY lane power to Disable state. */
@@ -3052,10 +3046,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, 
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,

				   struct intel_cx0pll_state *pll_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);

	else

		intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
@@ -3064,10 +3055,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,

				 const struct intel_cx0pll_state *pll_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);



	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
@@ -3133,7 +3121,6 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state, 
		intel_atomic_get_new_crtc_state(state, crtc);

	struct intel_encoder *encoder;

	struct intel_cx0pll_state mpll_hw_state = {};

	enum phy phy;



	if (DISPLAY_VER(i915) < 14)

		return;
@@ -3147,14 +3134,13 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state, 
		return;



	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);

	phy = intel_port_to_phy(i915, encoder->port);



	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))

		return;



	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);

	else

		intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20);

drivers/gpu/drm/i915/display/intel_ddi.c

+47 −69

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

+5 −9
Original line number Diff line number Diff line
@@ -1691,14 +1691,11 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder, 
		      const struct intel_crtc_state *crtc_state,

		      int *n_entries)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000)

		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);

	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))

	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_encoder_is_c10phy(encoder)))

		return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);

	else if (!intel_is_c10phy(i915, phy))

	else if (!intel_encoder_is_c10phy(encoder))

		return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);

	else

		return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries);
@@ -1707,14 +1704,13 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder, 
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);



	if (DISPLAY_VER(i915) >= 14) {

		encoder->get_buf_trans = mtl_get_cx0_buf_trans;

	} else if (IS_DG2(i915)) {

		encoder->get_buf_trans = dg2_get_snps_buf_trans;

	} else if (IS_ALDERLAKE_P(i915)) {

		if (intel_phy_is_combo(i915, phy))

		if (intel_encoder_is_combo(encoder))

			encoder->get_buf_trans = adlp_get_combo_buf_trans;

		else

			encoder->get_buf_trans = adlp_get_dkl_buf_trans;
@@ -1725,7 +1721,7 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) 
	} else if (IS_DG1(i915)) {

		encoder->get_buf_trans = dg1_get_combo_buf_trans;

	} else if (DISPLAY_VER(i915) >= 12) {

		if (intel_phy_is_combo(i915, phy))

		if (intel_encoder_is_combo(encoder))

			encoder->get_buf_trans = tgl_get_combo_buf_trans;

		else

			encoder->get_buf_trans = tgl_get_dkl_buf_trans;
@@ -1734,7 +1730,7 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) 
			encoder->get_buf_trans = jsl_get_combo_buf_trans;

		else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))

			encoder->get_buf_trans = ehl_get_combo_buf_trans;

		else if (intel_phy_is_combo(i915, phy))

		else if (intel_encoder_is_combo(encoder))

			encoder->get_buf_trans = icl_get_combo_buf_trans;

		else

			encoder->get_buf_trans = icl_get_mg_buf_trans;

drivers/gpu/drm/i915/display/intel_display_power_well.c

+1 −1
Original line number Diff line number Diff line
@@ -251,7 +251,7 @@ static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, 
	 * as HDMI-only and routed to a combo PHY, the encoder either won't be

	 * present at all or it will not have an aux_ch assigned.

	 */

	return dig_port ? intel_port_to_phy(i915, dig_port->base.port) : PHY_NONE;

	return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;

}



static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_dp.c

+5 −10
Original line number Diff line number Diff line
@@ -443,11 +443,9 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp) 


static int icl_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;



	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))

	if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))

		return 540000;



	return 810000;
@@ -463,11 +461,9 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp) 


static int mtl_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;



	if (intel_is_c10phy(i915, phy))

	if (intel_encoder_is_c10phy(encoder))

		return 810000;



	return 2000000;
@@ -6596,7 +6592,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, 
	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum port port = intel_encoder->port;

	enum phy phy = intel_port_to_phy(dev_priv, port);

	int type;



	/* Initialize the work for modeset in case of link train failure */
@@ -6621,7 +6616,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, 
		 * Currently we don't support eDP on TypeC ports, although in

		 * theory it could work on TypeC legacy ports.

		 */

		drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));

		drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder));

		type = DRM_MODE_CONNECTOR_eDP;

		intel_encoder->type = INTEL_OUTPUT_EDP;