Commit 7fdaba91 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'rtc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux 

Pull RTC updates from Alexandre Belloni:
 "There are two new drivers this cycle. There is also support for a
  negative offset for RTCs that have been shipped with a date set using
  an epoch that is before 1970. This unfortunately happens with some
  products that ship with a vendor kernel and an out of tree driver.

  Core:
   - support negative offsets for RTCs that have shipped with an epoch
     earlier than 1970

  New drivers:
   - NXP S32G2/S32G3
   - Sophgo CV1800

  Drivers:
   - loongson: fix missing alarm notifications for ACPI
   - m41t80: kickstart ocillator upon failure
   - mt6359: mt6357 support
   - pcf8563: fix wrong alarm register
   - sh: cleanups"

* tag 'rtc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (39 commits)
  rtc: mt6359: Add mt6357 support
  rtc: test: Test date conversion for dates starting in 1900
  rtc: test: Also test time and wday outcome of rtc_time64_to_tm()
  rtc: test: Emit the seconds-since-1970 value instead of days-since-1970
  rtc: Fix offset calculation for .start_secs < 0
  rtc: Make rtc_time64_to_tm() support dates before 1970
  rtc: pcf8563: fix wrong alarm register
  rtc: rzn1: support input frequencies other than 32768Hz
  rtc: rzn1: Disable controller before initialization
  dt-bindings: rtc: rzn1: add optional second clock
  rtc: m41t80: reduce verbosity
  rtc: m41t80: kickstart ocillator upon failure
  rtc: s32g: add NXP S32G2/S32G3 SoC support
  dt-bindings: rtc: add schema for NXP S32G2/S32G3 SoCs
  dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
  dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
  rtc: loongson: Add missing alarm notifications for ACPI RTC events
  rtc: sophgo: add rtc support for Sophgo CV1800 SoC
  rtc: stm32: drop unused module alias
  rtc: s3c: drop unused module alias
  ...
parents bfdf35c5 3d8b44b1

Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml

+3 −1
Original line number Diff line number Diff line
@@ -23,7 +23,9 @@ properties: 
          - microchip,sam9x60-rtc

          - microchip,sama7g5-rtc

      - items:

          - const: microchip,sam9x7-rtc

          - enum:

              - microchip,sam9x7-rtc

              - microchip,sama7d65-rtc

          - const: microchip,sam9x60-rtc



  reg:

Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ properties: 
          - enum:

              - microchip,sam9x60-rtt

              - microchip,sam9x7-rtt

              - microchip,sama7d65-rtt

          - const: atmel,at91sam9260-rtt

      - items:

          - const: microchip,sama7g5-rtt

Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml

0 → 100644
+72 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP S32G2/S32G3 Real Time Clock (RTC)



maintainers:

  - Bogdan Hamciuc <bogdan.hamciuc@nxp.com>

  - Ciprian Marian Costea <ciprianmarian.costea@nxp.com>



description:

  RTC hardware module present on S32G2/S32G3 SoCs is used as a wakeup source.

  It is not kept alive during system reset and it is not battery-powered.



allOf:

  - $ref: rtc.yaml#



properties:

  compatible:

    oneOf:

      - enum:

          - nxp,s32g2-rtc

      - items:

          - const: nxp,s32g3-rtc

          - const: nxp,s32g2-rtc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: ipg clock drives the access to the RTC iomapped registers

      - description: Clock source for the RTC module. Can be selected between

          4 different clock sources using an integrated hardware mux.

          On S32G2/S32G3 SoCs, 'source0' is the SIRC clock (~32KHz) and it is

          available during standby and runtime. 'source1' is reserved and cannot

          be used. 'source2' is the FIRC clock and it is only available during

          runtime providing a better resolution (~48MHz). 'source3' is an external

          RTC clock source which can be additionally added in hardware.



  clock-names:

    items:

      - const: ipg

      - enum: [ source0, source1, source2, source3 ]



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    rtc@40060000 {

        compatible = "nxp,s32g3-rtc",

                     "nxp,s32g2-rtc";

        reg = <0x40060000 0x1000>;

        interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks 54>, <&clks 55>;

        clock-names = "ipg", "source0";

    };

Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml

+6 −0
Original line number Diff line number Diff line
@@ -55,6 +55,12 @@ properties: 
    description:

      RTC alarm is not owned by the OS



  qcom,uefi-rtc-info:

    type: boolean

    description:

      RTC offset is stored as a four-byte GPS time offset in a 12-byte UEFI

      variable 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo



  wakeup-source: true



required:

Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml

+6 −2
Original line number Diff line number Diff line
@@ -33,10 +33,14 @@ properties: 
      - const: pps



  clocks:

    maxItems: 1

    minItems: 1

    maxItems: 2



  clock-names:

    const: hclk

    minItems: 1

    items:

      - const: hclk

      - const: xtal



  power-domains:

    maxItems: 1