Commit 7fe722ee authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio 



Enable HDMI audio on the RZ/G2LC SMARC EVK.  Set SW 1.5 on the SoM
module to the OFF position to turn on HDMI audio.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240826090803.56176-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 73573fde

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts

+3 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ 
#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"

#endif



/* Please set SW_I2S0_I2S1. Default value is 0 */

#define SW_I2S0_I2S1   0



#include "r9a07g044c2.dtsi"

#include "rzg2lc-smarc-som.dtsi"

#include "rzg2lc-smarc.dtsi"

arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -33,6 +33,16 @@ hdmi_con_out: endpoint { 
			};

		};

	};



#if (SW_I2S0_I2S1)

	/delete-node/ sound;



	sound_card {

		compatible = "audio-graph-card";

		label = "HDMI-Audio";

		dais = <&i2s2_port>;

	};

#endif

};



#if (SW_SCIF_CAN || SW_RSPI_CAN)
@@ -48,9 +58,11 @@ &canfd { 
};

#endif



#if (!SW_I2S0_I2S1)

&cpu_dai {

	sound-dai = <&ssi0>;

};

#endif



&dsi {

	status = "okay";
@@ -104,6 +116,15 @@ adv7535_out: endpoint { 
					remote-endpoint = <&hdmi_con_out>;

				};

			};



#if (SW_I2S0_I2S1)

			port@2 {

				reg = <2>;

				codec_endpoint: endpoint {

					remote-endpoint = <&i2s2_cpu_endpoint>;

				};

			};

#endif

		};

	};

};
@@ -177,6 +198,18 @@ &ssi0 { 
	pinctrl-names = "default";



	status = "okay";



#if (SW_I2S0_I2S1)

	i2s2_port: port {

		i2s2_cpu_endpoint: endpoint {

			remote-endpoint = <&codec_endpoint>;

			dai-format = "i2s";



			bitclock-master = <&i2s2_cpu_endpoint>;

			frame-master = <&i2s2_cpu_endpoint>;

		};

	};

#endif

};



#if (SW_RSPI_CAN)