Commit 805f9a06 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.19-2026-01-02' of... 

Merge tag 'perf-tools-fixes-for-v6.19-2026-01-02' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tool fixes and from Namhyung Kim:

 - skip building BPF skeletons if libopenssl is missing

 - a couple of test updates

 - handle error cases of filename__read_build_id()

 - support NVIDIA Olympus for ARM SPE profiling

 - update tool headers to sync with the kernel

* tag 'perf-tools-fixes-for-v6.19-2026-01-02' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  tools build: Fix the common set of features test wrt libopenssl
  tools headers: Sync syscall table with kernel sources
  tools headers: Sync linux/socket.h with kernel sources
  tools headers: Sync linux/gfp_types.h with kernel sources
  tools headers: Sync arm64 headers with kernel sources
  tools headers: Sync x86 headers with kernel sources
  tools headers: Sync UAPI sound/asound.h with kernel sources
  tools headers: Sync UAPI linux/mount.h with kernel sources
  tools headers: Sync UAPI linux/fs.h with kernel sources
  tools headers: Sync UAPI linux/fcntl.h with kernel sources
  tools headers: Sync UAPI KVM headers with kernel sources
  tools headers: Sync UAPI drm/drm.h with kernel sources
  perf arm-spe: Add NVIDIA Olympus to neoverse list
  tools headers arm64: Add NVIDIA Olympus part
  perf tests top: Make the test exclusive
  perf tests kvm: Avoid leaving perf.data.guest file around
  perf symbol: Fix ENOENT case for filename__read_build_id
  perf tools: Disable BPF skeleton if no libopenssl found
  tools/build: Add a feature test for libopenssl
parents bbbc7210 fe072f65

tools/arch/arm64/include/asm/cputype.h

+5 −3
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ 
#define ARM_CPU_PART_CORTEX_A78AE	0xD42

#define ARM_CPU_PART_CORTEX_X1		0xD44

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_X1C		0xD4C

#define ARM_CPU_PART_CORTEX_A520	0xD80

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_A715	0xD4D
@@ -93,6 +92,7 @@ 
#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_A720	0xD81

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3AE	0xD83

#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define ARM_CPU_PART_CORTEX_X925	0xD85

#define ARM_CPU_PART_CORTEX_A725	0xD87
@@ -130,6 +130,7 @@ 


#define NVIDIA_CPU_PART_DENVER		0x003

#define NVIDIA_CPU_PART_CARMEL		0x004

#define NVIDIA_CPU_PART_OLYMPUS		0x010



#define FUJITSU_CPU_PART_A64FX		0x001
@@ -171,7 +172,6 @@ 
#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)

#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)

#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
@@ -183,6 +183,7 @@ 
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)

#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
@@ -222,6 +223,7 @@ 


#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
@@ -245,7 +247,7 @@ 
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_EL1_NFD1 | TCR_EL1_NFD0)



#ifndef __ASSEMBLER__

tools/arch/x86/include/asm/cpufeatures.h

+11 −0
Original line number Diff line number Diff line
@@ -314,6 +314,7 @@ 
#define X86_FEATURE_SM4			(12*32+ 2) /* SM4 instructions */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* "avx_vnni" AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */

#define X86_FEATURE_LASS		(12*32+ 6) /* "lass" Linear Address Space Separation */

#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */

#define X86_FEATURE_ARCH_PERFMON_EXT	(12*32+ 8) /* Intel Architectural PerfMon Extension */

#define X86_FEATURE_FZRM		(12*32+10) /* Fast zero-length REP MOVSB */
@@ -338,6 +339,7 @@ 
#define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */

#define X86_FEATURE_AMD_IBRS_SAME_MODE	(13*32+19) /* Indirect Branch Restricted Speculation same mode protection*/

#define X86_FEATURE_EFER_LMSLE_MBZ	(13*32+20) /* EFER.LMSLE must be zero */

#define X86_FEATURE_AMD_PPIN		(13*32+23) /* "amd_ppin" Protected Processor Inventory Number */

#define X86_FEATURE_AMD_SSBD		(13*32+24) /* Speculative Store Bypass Disable */

#define X86_FEATURE_VIRT_SSBD		(13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
@@ -502,6 +504,15 @@ 
#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */

#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */

#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */

#define X86_FEATURE_SGX_EUPDATESVN	(21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */



#define X86_FEATURE_SDCIAE		(21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */

#define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /*

						      * Clear CPU buffers before VM-Enter if the vCPU

						      * can access host MMIO (ignored for all intents

						      * and purposes if CLEAR_CPU_BUF_VM is set).

						      */

#define X86_FEATURE_X2AVIC_EXT		(21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */



/*

 * BUG word(s)

tools/arch/x86/include/asm/msr-index.h

+30 −0
Original line number Diff line number Diff line
@@ -166,6 +166,10 @@ 
						 * Processor MMIO stale data

						 * vulnerabilities.

						 */

#define ARCH_CAP_MCU_ENUM		BIT(16) /*

						 * Indicates the presence of microcode update

						 * feature enumeration and status information.

						 */

#define ARCH_CAP_FB_CLEAR		BIT(17)	/*

						 * VERW clears CPU fill buffer

						 * even on MDS_NO CPUs.
@@ -327,6 +331,26 @@ 
					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \

					 PERF_CAP_PEBS_TIMING_INFO)



/* Arch PEBS */

#define MSR_IA32_PEBS_BASE		0x000003f4

#define MSR_IA32_PEBS_INDEX		0x000003f5

#define ARCH_PEBS_OFFSET_MASK		0x7fffff

#define ARCH_PEBS_INDEX_WR_SHIFT	4



#define ARCH_PEBS_RELOAD		0xffffffff

#define ARCH_PEBS_CNTR_ALLOW		BIT_ULL(35)

#define ARCH_PEBS_CNTR_GP		BIT_ULL(36)

#define ARCH_PEBS_CNTR_FIXED		BIT_ULL(37)

#define ARCH_PEBS_CNTR_METRICS		BIT_ULL(38)

#define ARCH_PEBS_LBR_SHIFT		40

#define ARCH_PEBS_LBR			(0x3ull << ARCH_PEBS_LBR_SHIFT)

#define ARCH_PEBS_VECR_XMM		BIT_ULL(49)

#define ARCH_PEBS_GPR			BIT_ULL(61)

#define ARCH_PEBS_AUX			BIT_ULL(62)

#define ARCH_PEBS_EN			BIT_ULL(63)

#define ARCH_PEBS_CNTR_MASK		(ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \

					 ARCH_PEBS_CNTR_METRICS)



#define MSR_IA32_RTIT_CTL		0x00000570

#define RTIT_CTL_TRACEEN		BIT(0)

#define RTIT_CTL_CYCLEACC		BIT(1)
@@ -929,6 +953,10 @@ 
#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)



#define MSR_IA32_UCODE_WRITE		0x00000079



#define MSR_IA32_MCU_ENUMERATION	0x0000007b

#define MCU_STAGING			BIT(4)



#define MSR_IA32_UCODE_REV		0x0000008b



/* Intel SGX Launch Enclave Public Key Hash MSRs */
@@ -1226,6 +1254,8 @@ 
#define MSR_IA32_VMX_VMFUNC             0x00000491

#define MSR_IA32_VMX_PROCBASED_CTLS3	0x00000492



#define MSR_IA32_MCU_STAGING_MBOX_ADDR	0x000007a5



/* Resctrl MSRs: */

/* - Intel: */

#define MSR_IA32_L3_QOS_CFG		0xc81

tools/arch/x86/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -502,6 +502,7 @@ struct kvm_sync_regs { 
/* vendor-specific groups and attributes for system fd */

#define KVM_X86_GRP_SEV			1

#  define KVM_X86_SEV_VMSA_FEATURES	0

#  define KVM_X86_SNP_POLICY_BITS	1



struct kvm_vmx_nested_state_data {

	__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];

tools/build/Makefile.feature

+4 −2
Original line number Diff line number Diff line
@@ -99,7 +99,8 @@ FEATURE_TESTS_BASIC := \ 
        libzstd				\

        disassembler-four-args		\

        disassembler-init-styled	\

        file-handle

        file-handle			\

        libopenssl



# FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list

# of all feature tests
@@ -147,7 +148,8 @@ FEATURE_DISPLAY ?= \ 
         lzma                   \

         bpf			\

         libaio			\

         libzstd

         libzstd		\

         libopenssl



#

# Declare group members of a feature to display the logical OR of the detection