Commit 80669042 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-05-08' of... 

Merge tag 'drm-intel-next-2025-05-08' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Non-display related:
- Fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'

Display related:
- More work towards display separation (Jani)
- Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwards (Jouni)
- DSC checks for 3 engines (Ankit)
- Add link rate and lane count to i915_display_info (Khaled)
- PSR fixes and workaround for underrun on idle (Jouni)
- LOBF enablement and ALMP fixes (Animesh)
- Clean up VGA plane handling (Ville)
- Use an intel_connector pointer everywhere (Imre)
- Fix warning for coffeelake on SunrisePoint PCH (Jiajia)
- Rework/Correction on minimum hblank calculation (Arun)
- Dmesg clean up (Jani)
- Add a couple of simple display workarounds (Ankit, Vinod)
- Refactor HDCP GSC (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/aByyL3bEufPu79OM@intel.com
parents 67322d35 ecd9352c

drivers/gpu/drm/display/drm_dp_helper.c

+34 −18
Original line number Diff line number Diff line
@@ -4393,8 +4393,9 @@ EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 
#endif



/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */

static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,

				     int symbol_size, bool is_mst)

static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels,

					  int bpp_x16, int symbol_size,

					  bool is_mst)

{

	int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);

	int align = is_mst ? 4 / lane_count : 1;
@@ -4402,22 +4403,42 @@ static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, 
	return ALIGN(cycles, align);

}



static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,

/**

 * drm_dp_link_symbol_cycles - calculate the link symbol count with/without dsc

 * @lane_count: DP link lane count

 * @pixels: number of pixels in a scanline

 * @dsc_slice_count: number of slices for DSC or '0' for non-DSC

 * @bpp_x16: bits per pixel in .4 binary fixed format

 * @symbol_size: DP symbol size

 * @is_mst: %true for MST and %false for SST

 *

 * Calculate the link symbol cycles for both DSC (@dsc_slice_count !=0) and

 * non-DSC case (@dsc_slice_count == 0) and return the count.

 */

int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,

			      int bpp_x16, int symbol_size, bool is_mst)

{

	int slice_count = dsc_slice_count ? : 1;

	int slice_pixels = DIV_ROUND_UP(pixels, slice_count);

	int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,

							  bpp_x16, symbol_size, is_mst);

	int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;

	int slice_data_cycles = drm_dp_link_data_symbol_cycles(lane_count,

							       slice_pixels,

							       bpp_x16,

							       symbol_size,

							       is_mst);

	int slice_eoc_cycles = 0;



	if (dsc_slice_count)

		slice_eoc_cycles = is_mst ? 4 / lane_count : 1;



	return slice_count * (slice_data_cycles + slice_eoc_cycles);

}

EXPORT_SYMBOL(drm_dp_link_symbol_cycles);



/**

 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream

 * @lane_count: DP link lane count

 * @hactive: pixel count of the active period in one scanline of the stream

 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set

 * @dsc_slice_count: number of slices for DSC or '0' for non-DSC

 * @bpp_x16: bits per pixel in .4 binary fixed point

 * @flags: DRM_DP_OVERHEAD_x flags

 *
@@ -4431,7 +4452,7 @@ static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_c 
 * as well as the stream's

 * - @hactive timing

 * - @bpp_x16 color depth

 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).

 * - compression mode (@dsc_slice_count != 0)

 * Note that this overhead doesn't account for the 8b/10b, 128b/132b

 * channel coding efficiency, for that see

 * @drm_dp_link_bw_channel_coding_efficiency().
@@ -4486,13 +4507,8 @@ int drm_dp_bw_overhead(int lane_count, int hactive, 
	WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&

		(flags & DRM_DP_BW_OVERHEAD_FEC));



	if (flags & DRM_DP_BW_OVERHEAD_DSC)

		symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,

							      dsc_slice_count,

							      bpp_x16, symbol_size,

							      is_mst);

	else

	symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,

						  dsc_slice_count,

						  bpp_x16, symbol_size,

						  is_mst);

drivers/gpu/drm/i915/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ i915-y += \ 
i915-y += \

	soc/intel_dram.o \

	soc/intel_gmch.o \

	soc/intel_pch.o \

	soc/intel_rom.o



# core library code
@@ -282,6 +281,7 @@ i915-y += \ 
	display/intel_modeset_setup.o \

	display/intel_modeset_verify.o \

	display/intel_overlay.o \

	display/intel_pch.o \

	display/intel_pch_display.o \

	display/intel_pch_refclk.o \

	display/intel_plane_initial.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+24 −36
Original line number Diff line number Diff line
@@ -7,9 +7,11 @@ 


#include <linux/string_helpers.h>



#include <drm/drm_print.h>



#include "g4x_dp.h"

#include "i915_drv.h"

#include "i915_reg.h"

#include "i915_utils.h"

#include "intel_audio.h"

#include "intel_backlight.h"

#include "intel_connector.h"
@@ -28,7 +30,6 @@ 
#include "intel_hotplug.h"

#include "intel_pch_display.h"

#include "intel_pps.h"

#include "vlv_sideband.h"



static const struct dpll g4x_dpll[] = {

	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
@@ -60,14 +61,13 @@ static void g4x_dp_set_clock(struct intel_encoder *encoder, 
			     struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	const struct dpll *divisor = NULL;

	int i, count = 0;



	if (display->platform.g4x) {

		divisor = g4x_dpll;

		count = ARRAY_SIZE(g4x_dpll);

	} else if (HAS_PCH_SPLIT(dev_priv)) {

	} else if (HAS_PCH_SPLIT(display)) {

		divisor = pch_dpll;

		count = ARRAY_SIZE(pch_dpll);

	} else if (display->platform.cherryview) {
@@ -93,7 +93,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
			     const struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	enum port port = encoder->port;

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -141,7 +140,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
			intel_dp->DP |= DP_ENHANCED_FRAMING;



		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

	} else if (HAS_PCH_CPT(display) && port != PORT_A) {

		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;



		intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
@@ -183,7 +182,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) 


static void assert_edp_pll(struct intel_display *display, bool state)

{

	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;

	bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;



	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,

				 "eDP PLL state assertion failure (expected %s, current %s)\n",
@@ -205,12 +204,12 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",

		    pipe_config->port_clock);



	intel_dp->DP &= ~DP_PLL_FREQ_MASK;

	intel_dp->DP &= ~EDP_PLL_FREQ_MASK;



	if (pipe_config->port_clock == 162000)

		intel_dp->DP |= DP_PLL_FREQ_162MHZ;

		intel_dp->DP |= EDP_PLL_FREQ_162MHZ;

	else

		intel_dp->DP |= DP_PLL_FREQ_270MHZ;

		intel_dp->DP |= EDP_PLL_FREQ_270MHZ;



	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);
@@ -225,7 +224,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	if (display->platform.ironlake)

		intel_wait_for_vblank_if_active(display, !crtc->pipe);



	intel_dp->DP |= DP_PLL_ENABLE;

	intel_dp->DP |= EDP_PLL_ENABLE;



	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);
@@ -243,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, 


	drm_dbg_kms(display->drm, "disabling eDP PLL\n");



	intel_dp->DP &= ~DP_PLL_ENABLE;

	intel_dp->DP &= ~EDP_PLL_ENABLE;



	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);
@@ -277,7 +276,6 @@ bool g4x_dp_port_enabled(struct intel_display *display, 
			 i915_reg_t dp_reg, enum port port,

			 enum pipe *pipe)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	bool ret;

	u32 val;
@@ -287,13 +285,13 @@ bool g4x_dp_port_enabled(struct intel_display *display, 


	/* asserts want to know the pipe even if the port is disabled */

	if (display->platform.ivybridge && port == PORT_A)

		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;

	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)

		*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);

	else if (HAS_PCH_CPT(display) && port != PORT_A)

		ret &= cpt_dp_port_selected(display, port, pipe);

	else if (display->platform.cherryview)

		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;

		*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);

	else

		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;

		*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);



	return ret;

}
@@ -338,7 +336,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
				struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 tmp, flags = 0;

	enum port port = encoder->port;
@@ -353,7 +350,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 


	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;



	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

	if (HAS_PCH_CPT(display) && port != PORT_A) {

		u32 trans_dp = intel_de_read(display,

					     TRANS_DP_CTL(crtc->pipe));
@@ -389,13 +386,12 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
	if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)

		pipe_config->limited_color_range = true;



	pipe_config->lane_count =

		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

	pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;



	g4x_dp_get_m_n(pipe_config);



	if (port == PORT_A) {

		if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)

		if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

			pipe_config->port_clock = 162000;

		else

			pipe_config->port_clock = 270000;
@@ -416,7 +412,6 @@ intel_dp_link_down(struct intel_encoder *encoder, 
		   const struct intel_crtc_state *old_crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	enum port port = encoder->port;
@@ -429,7 +424,7 @@ intel_dp_link_down(struct intel_encoder *encoder, 
	drm_dbg_kms(display->drm, "\n");



	if ((display->platform.ivybridge && port == PORT_A) ||

	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {

	    (HAS_PCH_CPT(display) && port != PORT_A)) {

		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

	} else {
@@ -448,7 +443,7 @@ intel_dp_link_down(struct intel_encoder *encoder, 
	 * to transcoder A after disabling it to allow the

	 * matching HDMI port to be enabled on transcoder A.

	 */

	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {

	if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {

		/*

		 * We get CPU/PCH FIFO underruns on the other pipe when

		 * doing the workaround. Sweep them under the rug.
@@ -581,16 +576,10 @@ static void chv_post_disable_dp(struct intel_atomic_state *state, 
				const struct intel_crtc_state *old_crtc_state,

				const struct drm_connector_state *old_conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	intel_dp_link_down(encoder, old_crtc_state);



	vlv_dpio_get(dev_priv);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, old_crtc_state, true);



	vlv_dpio_put(dev_priv);

}



static void
@@ -1223,10 +1212,10 @@ static int g4x_dp_compute_config(struct intel_encoder *encoder, 
				 struct intel_crtc_state *crtc_state,

				 struct drm_connector_state *conn_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	int ret;



	if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A)

	if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A)

		crtc_state->has_pch_encoder = true;



	ret = intel_dp_compute_config(encoder, crtc_state, conn_state);
@@ -1279,7 +1268,6 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { 
bool g4x_dp_init(struct intel_display *display,

		 i915_reg_t output_reg, enum port port)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	const struct intel_bios_encoder_data *devdata;

	struct intel_digital_port *dig_port;

	struct intel_encoder *intel_encoder;
@@ -1353,7 +1341,7 @@ bool g4x_dp_init(struct intel_display *display, 
	intel_encoder->audio_disable = g4x_dp_audio_disable;



	if ((display->platform.ivybridge && port == PORT_A) ||

	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))

	    (HAS_PCH_CPT(display) && port != PORT_A))

		dig_port->dp.set_link_train = cpt_set_link_train;

	else

		dig_port->dp.set_link_train = g4x_set_link_train;
@@ -1370,7 +1358,7 @@ bool g4x_dp_init(struct intel_display *display, 
		intel_encoder->set_signal_levels = g4x_set_signal_levels;



	if (display->platform.valleyview || display->platform.cherryview ||

	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {

	    (HAS_PCH_SPLIT(display) && port != PORT_A)) {

		dig_port->dp.preemph_max = intel_dp_preemph_max_3;

		dig_port->dp.voltage_max = intel_dp_voltage_max_3;

	} else {

drivers/gpu/drm/i915/display/g4x_hdmi.c

+10 −22
Original line number Diff line number Diff line
@@ -5,8 +5,9 @@ 
 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).

 */



#include <drm/drm_print.h>



#include "g4x_hdmi.h"

#include "i915_drv.h"

#include "i915_reg.h"

#include "intel_atomic.h"

#include "intel_audio.h"
@@ -22,13 +23,11 @@ 
#include "intel_hdmi.h"

#include "intel_hotplug.h"

#include "intel_sdvo.h"

#include "vlv_sideband.h"



static void intel_hdmi_prepare(struct intel_encoder *encoder,

			       const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -37,7 +36,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, 
	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);



	hdmi_val = SDVO_ENCODING_HDMI;

	if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)

	if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)

		hdmi_val |= HDMI_COLOR_RANGE_16_235;

	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)

		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -52,7 +51,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, 
	if (crtc_state->has_hdmi_sink)

		hdmi_val |= HDMI_MODE_SELECT_HDMI;



	if (HAS_PCH_CPT(dev_priv))

	if (HAS_PCH_CPT(display))

		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);

	else if (display->platform.cherryview)

		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
@@ -134,9 +133,8 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 
	struct intel_display *display = to_intel_display(encoder);

	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);



	if (HAS_PCH_SPLIT(i915)) {

	if (HAS_PCH_SPLIT(display)) {

		crtc_state->has_pch_encoder = true;

		if (!intel_fdi_compute_pipe_bpp(crtc_state))

			return -EINVAL;
@@ -155,7 +153,6 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, 
				  struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	u32 tmp, flags = 0;

	int dotclock;
@@ -186,7 +183,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, 
	if (tmp & HDMI_AUDIO_ENABLE)

		pipe_config->has_audio = true;



	if (!HAS_PCH_SPLIT(dev_priv) &&

	if (!HAS_PCH_SPLIT(display) &&

	    tmp & HDMI_COLOR_RANGE_16_235)

		pipe_config->limited_color_range = true;
@@ -383,7 +380,6 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, 
			       const struct drm_connector_state *old_conn_state)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	struct intel_digital_port *dig_port =

		hdmi_to_dig_port(intel_hdmi);
@@ -401,7 +397,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, 
	 * to transcoder A after disabling it to allow the

	 * matching DP port to be enabled on transcoder A.

	 */

	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

	if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

		/*

		 * We get CPU/PCH FIFO underruns on the other pipe when

		 * doing the workaround. Sweep them under the rug.
@@ -539,15 +535,8 @@ static void chv_hdmi_post_disable(struct intel_atomic_state *state, 
				  const struct intel_crtc_state *old_crtc_state,

				  const struct drm_connector_state *old_conn_state)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	vlv_dpio_get(dev_priv);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, old_crtc_state, true);



	vlv_dpio_put(dev_priv);

}



static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
@@ -682,7 +671,6 @@ static bool assert_hdmi_port_valid(struct intel_display *display, enum port port 
bool g4x_hdmi_init(struct intel_display *display,

		   i915_reg_t hdmi_reg, enum port port)

{

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	const struct intel_bios_encoder_data *devdata;

	struct intel_digital_port *dig_port;

	struct intel_encoder *intel_encoder;
@@ -724,7 +712,7 @@ bool g4x_hdmi_init(struct intel_display *display, 


	intel_encoder->hotplug = intel_hdmi_hotplug;

	intel_encoder->compute_config = g4x_hdmi_compute_config;

	if (HAS_PCH_SPLIT(dev_priv)) {

	if (HAS_PCH_SPLIT(display)) {

		intel_encoder->disable = pch_disable_hdmi;

		intel_encoder->post_disable = pch_post_disable_hdmi;

	} else {
@@ -745,9 +733,9 @@ bool g4x_hdmi_init(struct intel_display *display, 
		intel_encoder->post_disable = vlv_hdmi_post_disable;

	} else {

		intel_encoder->pre_enable = intel_hdmi_pre_enable;

		if (HAS_PCH_CPT(dev_priv))

		if (HAS_PCH_CPT(display))

			intel_encoder->enable = cpt_enable_hdmi;

		else if (HAS_PCH_IBX(dev_priv))

		else if (HAS_PCH_IBX(display))

			intel_encoder->enable = ibx_enable_hdmi;

		else

			intel_encoder->enable = g4x_enable_hdmi;

drivers/gpu/drm/i915/display/i9xx_plane.c

+18 −25
Original line number Diff line number Diff line
@@ -7,9 +7,10 @@ 
#include <drm/drm_atomic_helper.h>

#include <drm/drm_blend.h>

#include <drm/drm_fourcc.h>

#include <drm/drm_print.h>



#include "i915_drv.h"

#include "i915_reg.h"

#include "i915_utils.h"

#include "i9xx_plane.h"

#include "i9xx_plane_regs.h"

#include "intel_atomic.h"
@@ -631,92 +632,84 @@ static void 
bdw_primary_enable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);

	enum pipe pipe = plane->pipe;



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

bdw_primary_disable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);

	enum pipe pipe = plane->pipe;



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

ivb_primary_enable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

ivb_primary_disable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

ilk_primary_enable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

ilk_primary_disable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

vlv_primary_enable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);

	enum pipe pipe = plane->pipe;



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static void

vlv_primary_disable_flip_done(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	struct drm_i915_private *i915 = to_i915(plane->base.dev);

	enum pipe pipe = plane->pipe;



	spin_lock_irq(&i915->irq_lock);

	spin_lock_irq(&display->irq.lock);

	i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

	spin_unlock_irq(&i915->irq_lock);

	spin_unlock_irq(&display->irq.lock);

}



static bool i9xx_plane_can_async_flip(u64 modifier)